seg7led.tan.qmsg

FPGA EP2C5Q288C8 IR-LED 原码,测试OK 打开即用.

{ "Info" "ITDB_TSU_RESULT" "irrecv:inst2\|ClkDevider\[14\] reset clk 9.461 ns register " "Info: tsu for register \"irrecv:inst2\|ClkDevider\[14\]\" (data pin = \"reset\", clock pin = \"clk\") is 9.461 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.623 ns + Longest pin register " "Info: + Longest pin to register delay is 9.623 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns reset 1 PIN PIN_206 46 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_206; Fanout = 46; PIN Node = 'reset'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 112 -64 104 128 "reset" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.059 ns) + CELL(0.370 ns) 8.433 ns irrecv:inst2\|ClkDevider\[10\]~274 2 COMB LCCOMB_X18_Y7_N14 15 " "Info: 2: + IC(7.059 ns) + CELL(0.370 ns) = 8.433 ns; Loc. = LCCOMB_X18_Y7_N14; Fanout = 15; COMB Node = 'irrecv:inst2\|ClkDevider\[10\]~274'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.429 ns" { reset irrecv:inst2|ClkDevider[10]~274 } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.530 ns) + CELL(0.660 ns) 9.623 ns irrecv:inst2\|ClkDevider\[14\] 3 REG LCFF_X19_Y7_N29 2 " "Info: 3: + IC(0.530 ns) + CELL(0.660 ns) = 9.623 ns; Loc. = LCFF_X19_Y7_N29; Fanout = 2; REG Node = 'irrecv:inst2\|ClkDevider\[14\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.190 ns" { irrecv:inst2|ClkDevider[10]~274 irrecv:inst2|ClkDevider[14] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.034 ns ( 21.14 % ) " "Info: Total cell delay = 2.034 ns ( 21.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.589 ns ( 78.86 % ) " "Info: Total interconnect delay = 7.589 ns ( 78.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.623 ns" { reset irrecv:inst2|ClkDevider[10]~274 irrecv:inst2|ClkDevider[14] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "9.623 ns" { reset {} reset~combout {} irrecv:inst2|ClkDevider[10]~274 {} irrecv:inst2|ClkDevider[14] {} } { 0.000ns 0.000ns 7.059ns 0.530ns } { 0.000ns 1.004ns 0.370ns 0.660ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 24 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clk clk~0 -2.203 ns - " "Info: - Offset between input clock \"clk\" and output clock \"clk~0\" is -2.203 ns" {  } { { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk~0 destination 2.325 ns - Shortest register " "Info: - Shortest clock path from clock \"clk~0\" to destination register is 2.325 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk~0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'clk~0'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk~0 } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns clk~0clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'clk~0clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { clk~0 clk~0clkctrl } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.822 ns) + CELL(0.666 ns) 2.325 ns irrecv:inst2\|ClkDevider\[14\] 3 REG LCFF_X19_Y7_N29 2 " "Info: 3: + IC(0.822 ns) + CELL(0.666 ns) = 2.325 ns; Loc. = LCFF_X19_Y7_N29; Fanout = 2; REG Node = 'irrecv:inst2\|ClkDevider\[14\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.488 ns" { clk~0clkctrl irrecv:inst2|ClkDevider[14] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 28.65 % ) " "Info: Total cell delay = 0.666 ns ( 28.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.659 ns ( 71.35 % ) " "Info: Total interconnect delay = 1.659 ns ( 71.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.325 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevider[14] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "2.325 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevider[14] {} } { 0.000ns 0.837ns 0.822ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.623 ns" { reset irrecv:inst2|ClkDevider[10]~274 irrecv:inst2|ClkDevider[14] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "9.623 ns" { reset {} reset~combout {} irrecv:inst2|ClkDevider[10]~274 {} irrecv:inst2|ClkDevider[14] {} } { 0.000ns 0.000ns 7.059ns 0.530ns } { 0.000ns 1.004ns 0.370ns 0.660ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.325 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevider[14] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "2.325 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevider[14] {} } { 0.000ns 0.837ns 0.822ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[6\] irrecv:inst2\|led\[4\] 14.977 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[6\]\" through register \"irrecv:inst2\|led\[4\]\" is 14.977 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk clk~0 -2.203 ns + " "Info: + Offset between input clock \"clk\" and output clock \"clk~0\" is -2.203 ns" {  } { { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk~0 source 5.971 ns + Longest register " "Info: + Longest clock path from clock \"clk~0\" to source register is 5.971 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk~0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'clk~0'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk~0 } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns clk~0clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'clk~0clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { clk~0 clk~0clkctrl } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.970 ns) 2.628 ns irrecv:inst2\|ClkDevideOut 3 REG LCFF_X18_Y7_N25 2 " "Info: 3: + IC(0.821 ns) + CELL(0.970 ns) = 2.628 ns; Loc. = LCFF_X18_Y7_N25; Fanout = 2; REG Node = 'irrecv:inst2\|ClkDevideOut'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.791 ns" { clk~0clkctrl irrecv:inst2|ClkDevideOut } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.828 ns) + CELL(0.000 ns) 4.456 ns irrecv:inst2\|ClkDevideOut~clkctrl 4 COMB CLKCTRL_G6 49 " "Info: 4: + IC(1.828 ns) + CELL(0.000 ns) = 4.456 ns; Loc. = CLKCTRL_G6; Fanout = 49; COMB Node = 'irrecv:inst2\|ClkDevideOut~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.849 ns) + CELL(0.666 ns) 5.971 ns irrecv:inst2\|led\[4\] 5 REG LCFF_X18_Y10_N5 7 " "Info: 5: + IC(0.849 ns) + CELL(0.666 ns) = 5.971 ns; Loc. = LCFF_X18_Y10_N5; Fanout = 7; REG Node = 'irrecv:inst2\|led\[4\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.515 ns" { irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|led[4] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 27.40 % ) " "Info: Total cell delay = 1.636 ns ( 27.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.335 ns ( 72.60 % ) " "Info: Total interconnect delay = 4.335 ns ( 72.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.971 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|led[4] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.971 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|led[4] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.849ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.905 ns + Longest register pin " "Info: + Longest register to pin delay is 10.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns irrecv:inst2\|led\[4\] 1 REG LCFF_X18_Y10_N5 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y10_N5; Fanout = 7; REG Node = 'irrecv:inst2\|led\[4\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { irrecv:inst2|led[4] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.929 ns) + CELL(0.206 ns) 2.135 ns segmain:inst1\|WideOr14~15 2 COMB LCCOMB_X18_Y10_N2 1 " "Info: 2: + IC(1.929 ns) + CELL(0.206 ns) = 2.135 ns; Loc. = LCCOMB_X18_Y10_N2; Fanout = 1; COMB Node = 'segmain:inst1\|WideOr14~15'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.135 ns" { irrecv:inst2|led[4] segmain:inst1|WideOr14~15 } "NODE_NAME" } } { "segmain.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/segmain.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.650 ns) 3.864 ns segmain:inst1\|Mux0~13 3 COMB LCCOMB_X18_Y10_N14 1 " "Info: 3: + IC(1.079 ns) + CELL(0.650 ns) = 3.864 ns; Loc. = LCCOMB_X18_Y10_N14; Fanout = 1; COMB Node = 'segmain:inst1\|Mux0~13'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.729 ns" { segmain:inst1|WideOr14~15 segmain:inst1|Mux0~13 } "NODE_NAME" } } { "segmain.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.592 ns) + CELL(0.370 ns) 4.826 ns segmain:inst1\|Mux0~14 4 COMB LCCOMB_X17_Y10_N12 1 " "Info: 4: + IC(0.592 ns) + CELL(0.370 ns) = 4.826 ns; Loc. = LCCOMB_X17_Y10_N12; Fanout = 1; COMB Node = 'segmain:inst1\|Mux0~14'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.962 ns" { segmain:inst1|Mux0~13 segmain:inst1|Mux0~14 } "NODE_NAME" } } { "segmain.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/segmain.v" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.983 ns) + CELL(3.096 ns) 10.905 ns seg_data\[6\] 5 PIN PIN_35 0 " "Info: 5: + IC(2.983 ns) + CELL(3.096 ns) = 10.905 ns; Loc. = PIN_35; Fanout = 0; PIN Node = 'seg_data\[6\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.079 ns" { segmain:inst1|Mux0~14 seg_data[6] } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 176 632 808 192 "seg_data\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.322 ns ( 39.63 % ) " "Info: Total cell delay = 4.322 ns ( 39.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.583 ns ( 60.37 % ) " "Info: Total interconnect delay = 6.583 ns ( 60.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.905 ns" { irrecv:inst2|led[4] segmain:inst1|WideOr14~15 segmain:inst1|Mux0~13 segmain:inst1|Mux0~14 seg_data[6] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "10.905 ns" { irrecv:inst2|led[4] {} segmain:inst1|WideOr14~15 {} segmain:inst1|Mux0~13 {} segmain:inst1|Mux0~14 {} seg_data[6] {} } { 0.000ns 1.929ns 1.079ns 0.592ns 2.983ns } { 0.000ns 0.206ns 0.650ns 0.370ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.971 ns" { clk~0 clk~0c