prev_cmp_seg7led.map.qmsg

FPGA EP2C5Q288C8 IR-LED 原码,测试OK 打开即用.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 29 20:08:32 2008 " "Info: Processing started: Thu May 29 20:08:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seg7led -c seg7led " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seg7led -c seg7led" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "irrecv.v(41) " "Warning (10268): Verilog HDL information at irrecv.v(41): Always Construct contains both blocking and non-blocking assignments" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 41 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "irrecv.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file irrecv.v" { { "Info" "ISGN_ENTITY_NAME" "1 irrecv " "Info: Found entity 1: irrecv" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7led.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file seg7led.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 seg7led " "Info: Found entity 1: seg7led" {  } { { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "segmain.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file segmain.v" { { "Info" "ISGN_ENTITY_NAME" "1 segmain " "Info: Found entity 1: segmain" {  } { { "segmain.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/segmain.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "seg7led " "Info: Elaborating entity \"seg7led\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "irrecv irrecv:inst2 " "Info: Elaborating entity \"irrecv\" for hierarchy \"irrecv:inst2\"" {  } { { "seg7led.bdf" "inst2" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 168 176 312 264 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "segmain segmain:inst1 " "Info: Elaborating entity \"segmain\" for hierarchy \"segmain:inst1\"" {  } { { "seg7led.bdf" "inst1" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 152 440 624 248 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}