prev_cmp_seg7led.qmsg

FPGA EP2C5Q288C8 IR-LED 原码,测试OK 打开即用.

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off seg7led -c seg7led " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off seg7led -c seg7led" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "134 " "Info: Allocated 134 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu May 29 20:08:52 2008 " "Info: Processing ended: Thu May 29 20:08:52 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 29 20:08:53 2008 " "Info: Processing started: Thu May 29 20:08:53 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off seg7led -c seg7led --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seg7led -c seg7led --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "irrecv:inst2\|ClkDevideOut " "Info: Detected ripple clock \"irrecv:inst2\|ClkDevideOut\" as buffer" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } } { "e:/programfile/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/programfile/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "irrecv:inst2\|ClkDevideOut" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk~0 register irrecv:inst2\|TimerCnt\[0\] register irrecv:inst2\|RecvState.STARTDOWN 14.675 ns " "Info: Slack time is 14.675 ns for clock \"clk~0\" between source register \"irrecv:inst2\|TimerCnt\[0\]\" and destination register \"irrecv:inst2\|RecvState.STARTDOWN\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "187.79 MHz 5.325 ns " "Info: Fmax is 187.79 MHz (period= 5.325 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "19.736 ns + Largest register register " "Info: + Largest register to register requirement is 19.736 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 17.797 ns " "Info: + Latch edge is 17.797 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk~0 20.000 ns -2.203 ns  50 " "Info: Clock period of Destination clock \"clk~0\" is 20.000 ns with  offset of -2.203 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.203 ns " "Info: - Launch edge is -2.203 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk~0 20.000 ns -2.203 ns  50 " "Info: Clock period of Source clock \"clk~0\" is 20.000 ns with  offset of -2.203 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk~0 destination 5.946 ns + Shortest register " "Info: + Shortest clock path from clock \"clk~0\" to destination register is 5.946 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk~0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'clk~0'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk~0 } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns clk~0clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'clk~0clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { clk~0 clk~0clkctrl } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.970 ns) 2.628 ns irrecv:inst2\|ClkDevideOut 3 REG LCFF_X18_Y7_N25 2 " "Info: 3: + IC(0.821 ns) + CELL(0.970 ns) = 2.628 ns; Loc. = LCFF_X18_Y7_N25; Fanout = 2; REG Node = 'irrecv:inst2\|ClkDevideOut'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.791 ns" { clk~0clkctrl irrecv:inst2|ClkDevideOut } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.828 ns) + CELL(0.000 ns) 4.456 ns irrecv:inst2\|ClkDevideOut~clkctrl 4 COMB CLKCTRL_G6 49 " "Info: 4: + IC(1.828 ns) + CELL(0.000 ns) = 4.456 ns; Loc. = CLKCTRL_G6; Fanout = 49; COMB Node = 'irrecv:inst2\|ClkDevideOut~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.824 ns) + CELL(0.666 ns) 5.946 ns irrecv:inst2\|RecvState.STARTDOWN 5 REG LCFF_X20_Y6_N31 2 " "Info: 5: + IC(0.824 ns) + CELL(0.666 ns) = 5.946 ns; Loc. = LCFF_X20_Y6_N31; Fanout = 2; REG Node = 'irrecv:inst2\|RecvState.STARTDOWN'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 27.51 % ) " "Info: Total cell delay = 1.636 ns ( 27.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.310 ns ( 72.49 % ) " "Info: Total interconnect delay = 4.310 ns ( 72.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|RecvState.STARTDOWN {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk~0 source 5.946 ns - Longest register " "Info: - Longest clock path from clock \"clk~0\" to source register is 5.946 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk~0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'clk~0'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk~0 } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.837 ns) + CELL(0.000 ns) 0.837 ns clk~0clkctrl 2 COMB CLKCTRL_G3 30 " "Info: 2: + IC(0.837 ns) + CELL(0.000 ns) = 0.837 ns; Loc. = CLKCTRL_G3; Fanout = 30; COMB Node = 'clk~0clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.837 ns" { clk~0 clk~0clkctrl } "NODE_NAME" } } { "seg7led.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/seg7led.bdf" { { 64 -64 104 80 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.970 ns) 2.628 ns irrecv:inst2\|ClkDevideOut 3 REG LCFF_X18_Y7_N25 2 " "Info: 3: + IC(0.821 ns) + CELL(0.970 ns) = 2.628 ns; Loc. = LCFF_X18_Y7_N25; Fanout = 2; REG Node = 'irrecv:inst2\|ClkDevideOut'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.791 ns" { clk~0clkctrl irrecv:inst2|ClkDevideOut } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.828 ns) + CELL(0.000 ns) 4.456 ns irrecv:inst2\|ClkDevideOut~clkctrl 4 COMB CLKCTRL_G6 49 " "Info: 4: + IC(1.828 ns) + CELL(0.000 ns) = 4.456 ns; Loc. = CLKCTRL_G6; Fanout = 49; COMB Node = 'irrecv:inst2\|ClkDevideOut~clkctrl'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.828 ns" { irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.824 ns) + CELL(0.666 ns) 5.946 ns irrecv:inst2\|TimerCnt\[0\] 5 REG LCFF_X20_Y6_N21 4 " "Info: 5: + IC(0.824 ns) + CELL(0.666 ns) = 5.946 ns; Loc. = LCFF_X20_Y6_N21; Fanout = 4; REG Node = 'irrecv:inst2\|TimerCnt\[0\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.490 ns" { irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|TimerCnt[0] } "NODE_NAME" } } { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 27.51 % ) " "Info: Total cell delay = 1.636 ns ( 27.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.310 ns ( 72.49 % ) " "Info: Total interconnect delay = 4.310 ns ( 72.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|TimerCnt[0] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|TimerCnt[0] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|RecvState.STARTDOWN {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|TimerCnt[0] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|TimerCnt[0] {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 148 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "irrecv.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/ir_7led/ir_7led/irrecv.v" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.946 ns" { clk~0 clk~0clkctrl irrecv:inst2|ClkDevideOut irrecv:inst2|ClkDevideOut~clkctrl irrecv:inst2|RecvState.STARTDOWN } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/programfile/altera/72/quartus/bin/Technology_Viewer.qrui" "5.946 ns" { clk~0 {} clk~0clkctrl {} irrecv:inst2|ClkDevideOut {} irrecv:inst2|ClkDevideOut~clkctrl {} irrecv:inst2|RecvState.STARTDOWN {} } { 0.000ns 0.837ns 0.821ns 1.828ns 0.824ns } { 0.000ns 0.000ns 0.970ns 0.000ns 0