i2c_fpga.map.qmsg

FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.

{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(383) " "Info (10264): Verilog HDL Case Statement information at i2c.v(383): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 383 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 i2c.v(714) " "Warning (10230): Verilog HDL assignment warning at i2c.v(714): truncated value with size 32 to match size of target (12)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 714 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(722) " "Info (10264): Verilog HDL Case Statement information at i2c.v(722): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 722 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(734) " "Warning (10270): Verilog HDL Case Statement warning at i2c.v(734): incomplete case statement has no default case item" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 734 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "seg_data i2c.v(732) " "Warning (10240): Verilog HDL Always Construct warning at i2c.v(732): inferring latch(es) for variable \"seg_data\", which holds its previous value in one or more paths through the always construct" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 732 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg_data\[0\] i2c.v(732) " "Info (10041): Inferred latch for \"seg_data\[0\]\" at i2c.v(732)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 732 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg_data\[1\] i2c.v(732) " "Info (10041): Inferred latch for \"seg_data\[1\]\" at i2c.v(732)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 732 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg_data\[2\] i2c.v(732) " "Info (10041): Inferred latch for \"seg_data\[2\]\" at i2c.v(732)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 732 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg_data\[3\] i2c.v(732) " "Info (10041): Inferred latch for \"seg_data\[3\]\" at i2c.v(732)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 732 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg_data\[4\] i2c.v(732) " "Info (10041): Inferred latch for \"seg_data\[4\]\" at i2c.v(732)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 732 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg_data\[5\] i2c.v(732) " "Info (10041): Inferred latch for \"seg_data\[5\]\" at i2c.v(732)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 732 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg_data\[6\] i2c.v(732) " "Info (10041): Inferred latch for \"seg_data\[6\]\" at i2c.v(732)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 732 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "seg_data\[7\] i2c.v(732) " "Info (10041): Inferred latch for \"seg_data\[7\]\" at i2c.v(732)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 732 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_test i2c_test:inst1 " "Info: Elaborating entity \"i2c_test\" for hierarchy \"i2c_test:inst1\"" {  } { { "I2C_FPGA.bdf" "inst1" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/I2C_FPGA.bdf" { { -8 392 552 88 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "delay_reset_block.bdf 1 1 " "Warning: Using design file delay_reset_block.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 delay_reset_block " "Info: Found entity 1: delay_reset_block" {  } { { "delay_reset_block.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/delay_reset_block.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "delay_reset_block delay_reset_block:inst2 " "Info: Elaborating entity \"delay_reset_block\" for hierarchy \"delay_reset_block:inst2\"" {  } { { "I2C_FPGA.bdf" "inst2" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/I2C_FPGA.bdf" { { 8 152 344 104 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "delay_reset_block " "Warning: Processing legacy GDF or BDF entity \"delay_reset_block\" with Max+Plus II bus and instance naming rules" {  } { { "delay_reset_block.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/delay_reset_block.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "reset_counter.v 1 1 " "Warning: Using design file reset_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 reset_counter " "Info: Found entity 1: reset_counter" {  } { { "reset_counter.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/reset_counter.v" 36 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reset_counter delay_reset_block:inst2\|reset_counter:inst " "Info: Elaborating entity \"reset_counter\" for hierarchy \"delay_reset_block:inst2\|reset_counter:inst\"" {  } { { "delay_reset_block.bdf" "inst" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/delay_reset_block.bdf" { { 224 688 832 336 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}