i2c_fpga.map.qmsg

FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 29 16:15:28 2008 " "Info: Processing started: Thu May 29 16:15:28 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off I2C_FPGA -c I2C_FPGA " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off I2C_FPGA -c I2C_FPGA" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "I2C_FPGA.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file I2C_FPGA.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 I2C_FPGA " "Info: Found entity 1: I2C_FPGA" {  } { { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/I2C_FPGA.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 14 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_test " "Info: Found entity 1: i2c_test" {  } { { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c_test.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "I2C_FPGA " "Info: Elaborating entity \"I2C_FPGA\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "I2C_FPGA " "Warning: Processing legacy GDF or BDF entity \"I2C_FPGA\" with Max+Plus II bus and instance naming rules" {  } { { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/I2C_FPGA.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c i2c:inst4 " "Info: Elaborating entity \"i2c\" for hierarchy \"i2c:inst4\"" {  } { { "I2C_FPGA.bdf" "inst4" { Schematic "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/I2C_FPGA.bdf" { { -40 624 808 88 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 i2c.v(79) " "Warning (10230): Verilog HDL assignment warning at i2c.v(79): truncated value with size 32 to match size of target (20)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 79 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 i2c.v(97) " "Warning (10230): Verilog HDL assignment warning at i2c.v(97): truncated value with size 32 to match size of target (8)" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 97 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(163) " "Info (10264): Verilog HDL Case Statement information at i2c.v(163): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 163 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(239) " "Info (10264): Verilog HDL Case Statement information at i2c.v(239): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 239 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(304) " "Info (10264): Verilog HDL Case Statement information at i2c.v(304): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 304 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(161) " "Info (10264): Verilog HDL Case Statement information at i2c.v(161): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 161 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(385) " "Info (10264): Verilog HDL Case Statement information at i2c.v(385): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 385 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(461) " "Info (10264): Verilog HDL Case Statement information at i2c.v(461): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 461 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(526) " "Info (10264): Verilog HDL Case Statement information at i2c.v(526): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 526 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(601) " "Info (10264): Verilog HDL Case Statement information at i2c.v(601): all case item expressions in this case statement are onehot" {  } { { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/ep2c5_project/I2C_test/i2c.v" 601 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "" 0}