i2c_fpga.hif

FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.

Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
11
920
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
I2C_FPGA
# storage
db|I2C_FPGA.(0).cnf
db|I2C_FPGA.(0).cnf
# case_insensitive
# source_file
I2C_FPGA.bdf
ee478a98fd2952e838c6d5c4bb8d3324
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# lmf
..|..|..|..|..|programfile|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
i2c
# storage
db|I2C_FPGA.(1).cnf
db|I2C_FPGA.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
i2c.v
a42a89503b64bfe9ce64c07b376b7dbf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
div_parameter
125
PARAMETER_SIGNED_DEC
DEF
start
0000
PARAMETER_UNSIGNED_BIN
DEF
first
0001
PARAMETER_UNSIGNED_BIN
DEF
second
0010
PARAMETER_UNSIGNED_BIN
DEF
third
0011
PARAMETER_UNSIGNED_BIN
DEF
fourth
0100
PARAMETER_UNSIGNED_BIN
DEF
fifth
0101
PARAMETER_UNSIGNED_BIN
DEF
sixth
0110
PARAMETER_UNSIGNED_BIN
DEF
seventh
0111
PARAMETER_UNSIGNED_BIN
DEF
eighth
1000
PARAMETER_UNSIGNED_BIN
DEF
ack
1001
PARAMETER_UNSIGNED_BIN
DEF
stop
1010
PARAMETER_UNSIGNED_BIN
DEF
ini
000
PARAMETER_UNSIGNED_BIN
DEF
sendaddr
001
PARAMETER_UNSIGNED_BIN
DEF
write_data
010
PARAMETER_UNSIGNED_BIN
DEF
read_data
011
PARAMETER_UNSIGNED_BIN
DEF
read_ini
000100
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
i2c:inst4
}
# lmf
..|..|..|..|..|programfile|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
i2c_test
# storage
db|I2C_FPGA.(2).cnf
db|I2C_FPGA.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
i2c_test.v
8790facb73b4a2f475cbafabd2b3a79f
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
i2c_test:inst1
}
# lmf
..|..|..|..|..|programfile|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
delay_reset_block
# storage
db|I2C_FPGA.(3).cnf
db|I2C_FPGA.(3).cnf
# case_insensitive
# source_file
delay_reset_block.bdf
ce2064e4f53d797a55cb77e6808e416f
25
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
delay_reset_block:inst2
delay_reset_block:inst3
}
# lmf
..|..|..|..|..|programfile|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
reset_counter
# storage
db|I2C_FPGA.(4).cnf
db|I2C_FPGA.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
reset_counter.v
699d56c194b081118191aa27c4d46c9d
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
delay_reset_block:inst2|reset_counter:inst
delay_reset_block:inst3|reset_counter:inst
}
# lmf
..|..|..|..|..|programfile|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
lpm_counter
# storage
db|I2C_FPGA.(5).cnf
db|I2C_FPGA.(5).cnf
# case_insensitive
# source_file
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|lpm_counter.tdf
f35217425caea2b1f2ce94448f6f2
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
10
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_p7j
PARAMETER_UNKNOWN
USR
}
# used_port {
q
-1
3
cout
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# include_file {
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|cmpconst.inc
e61874547688138e6fc0b49ff8760
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|lpm_counter.inc
7f888b135ddf66f0653c44cb18ac5
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|alt_synch_counter.inc
09966d10c3e95c888bf8e443df34d8
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|alt_counter_f10ke.inc
536f8da8218b4a93689416f9baea1880
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|alt_synch_counter_f.inc
93a5aae1d8bd19c9e8e8eef93ab2177d
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|aglobal72.inc
f39123b8592ab2dac019716e56b3ec18
..|..|..|..|..|programfile|altera|72|quartus|libraries|megafunctions|alt_counter_stratix.inc
2251b94d26afaa53635df1aff6b6e7be
}
# hierarchies {
delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component
delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component
}
# lmf
..|..|..|..|..|programfile|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
cntr_p7j
# storage
db|I2C_FPGA.(6).cnf
db|I2C_FPGA.(6).cnf
# case_insensitive
# source_file
db|cntr_p7j.tdf
13a565b64567519b4d65260c0e9d9e
6
# used_port {
q9
-1
3
q8
-1
3
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cout
-1
3
cnt_en
-1
3
clock
-1
3
aclr
-1
3
}
# hierarchies {
delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated
delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated
}
# lmf
..|..|..|..|..|programfile|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete