prev_cmp_i2c_fpga.fit.qmsg

FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.

{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.989 ns register register " "Info: Estimated most critical path is register to register delay of 0.989 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_test:inst1\|counter\[1\] 1 REG LAB_X13_Y7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X13_Y7; Fanout = 4; REG Node = 'i2c_test:inst1\|counter\[1\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c_test:inst1|counter[1] } "NODE_NAME" } } { "i2c_test.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c_test.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.624 ns) 0.881 ns i2c:inst4\|writeData_reg~445 2 COMB LAB_X13_Y7 1 " "Info: 2: + IC(0.257 ns) + CELL(0.624 ns) = 0.881 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'i2c:inst4\|writeData_reg~445'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.881 ns" { i2c_test:inst1|counter[1] i2c:inst4|writeData_reg~445 } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 0.989 ns i2c:inst4\|writeData_reg\[1\] 3 REG LAB_X13_Y7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 0.989 ns; Loc. = LAB_X13_Y7; Fanout = 2; REG Node = 'i2c:inst4\|writeData_reg\[1\]'" {  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { i2c:inst4|writeData_reg~445 i2c:inst4|writeData_reg[1] } "NODE_NAME" } } { "i2c.v" "" { Text "E:/project/qii/yg2c58eb/I2C_test/i2c.v" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.732 ns ( 74.01 % ) " "Info: Total cell delay = 0.732 ns ( 74.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.257 ns ( 25.99 % ) " "Info: Total interconnect delay = 0.257 ns ( 25.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.989 ns" { i2c_test:inst1|counter[1] i2c:inst4|writeData_reg~445 i2c:inst4|writeData_reg[1] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X14_Y0 X28_Y14 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X14_Y0 to location X28_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "12 " "Warning: Found 12 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "scl 0 " "Info: Pin \"scl\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_com\[1\] 0 " "Info: Pin \"seg_com\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_com\[0\] 0 " "Info: Pin \"seg_com\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[7\] 0 " "Info: Pin \"seg_data\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[6\] 0 " "Info: Pin \"seg_data\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[5\] 0 " "Info: Pin \"seg_data\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[4\] 0 " "Info: Pin \"seg_data\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[3\] 0 " "Info: Pin \"seg_data\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[2\] 0 " "Info: Pin \"seg_data\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[1\] 0 " "Info: Pin \"seg_data\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "seg_data\[0\] 0 " "Info: Pin \"seg_data\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sda 0 " "Info: Pin \"sda\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seg_data\[7\] VCC " "Info: Pin seg_data\[7\] has VCC driving its datain port" {  } { { "e:/programfile/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/programfile/altera/72/quartus/bin/pin_planner.ppl" { seg_data[7] } } } { "e:/programfile/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/programfile/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "seg_data\[7\]" } } } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { 32 848 1024 48 "seg_data\[7..0\]" "" } } } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { seg_data[7] } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { seg_data[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "i2c:inst4\|link " "Info: Following pins have the same output enable: i2c:inst4\|link" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional sda 3.3-V LVTTL " "Info: Type bidirectional pin sda uses the 3.3-V LVTTL I/O standard" {  } { { "e:/programfile/altera/72/quartus/bin/pin_planner.ppl" "" { PinPlanner "e:/programfile/altera/72/quartus/bin/pin_planner.ppl" { sda } } } { "e:/programfile/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/programfile/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sda" } } } } { "I2C_FPGA.bdf" "" { Schematic "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.bdf" { { 0 848 1024 16 "sda" "" } } } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } } { "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/programfile/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sda } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0 "" 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0 "" 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.fit.smsg " "Info: Generated suppressed messages file E:/project/qii/yg2c58eb/I2C_test/I2C_FPGA.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "171 " "Info: Allocated 171 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 19 15:40:30 2008 " "Info: Processing ended: Mon May 19 15:40:30 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}