i2c_fpga.fit.eqn

FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.

D1L65 = D1L62 & (D1L64 & (D1L285) # !D1L64 & D1L57) # !D1L62 & (D1L64);


--D1L66 is i2c:inst4|Select~12585 at LC_X8_Y6_N9
--operation mode is normal

D1L66 = D1_i2c_state.write_data & D1_inner_state.eighth;


--D1L67 is i2c:inst4|Select~12586 at LC_X7_Y6_N4
--operation mode is normal

D1L67 = D1L66 & (D1_inner_state.ack # D1_phase3) # !D1L66 & (D1L65);


--D1L68 is i2c:inst4|Select~12587 at LC_X9_Y6_N6
--operation mode is normal

D1L68 = !D1_i2c_state.write_data & !D1_i2c_state.read_data;


--D1L69 is i2c:inst4|Select~12588 at LC_X9_Y6_N2
--operation mode is normal

D1L69 = D1L50 & (!D1L68 & D1_i2c_state.sendaddr # !D1_i2c_state.ini) # !D1L50 & (D1_i2c_state.sendaddr);


--D1L70 is i2c:inst4|Select~12589 at LC_X9_Y6_N1
--operation mode is normal

D1L70 = D1_phase3 & (D1_inner_state.ack & (!D1_i2c_state.ini) # !D1_inner_state.ack & D1_i2c_state.sendaddr) # !D1_phase3 & D1_i2c_state.sendaddr;


--D1L273 is i2c:inst4|i2c_state~243 at LC_X9_Y5_N1
--operation mode is normal

D1L273 = !D1_i2c_state.ini & (D1_i2c_state.read_ini & !D1_main_state.10 # !D1L55);


--D1L14 is i2c:inst4|Equal~736 at LC_X6_Y7_N4
--operation mode is normal

D1L14 = D1L8 & D1L12 & !D1_clk_div[6] & D1L13;


--G1_safe_q[9] is delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[9] at LC_X14_Y6_N4
--operation mode is arithmetic

G1_safe_q[9]_carry_eqn = (!G1L14 & G1L25) # (G1L14 & G1L26);
G1_safe_q[9]_lut_out = G1_safe_q[9] $ (!G1_cout & G1_safe_q[9]_carry_eqn);
G1_safe_q[9] = DFFEAS(G1_safe_q[9]_lut_out, GLOBAL(clk), write, , , , , , );

--G1L28 is delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT at LC_X14_Y6_N4
--operation mode is arithmetic

G1L28 = CARRY(!G1L26 # !G1_safe_q[9]);


--G2_safe_q[9] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[9] at LC_X12_Y6_N4
--operation mode is arithmetic

G2_safe_q[9]_carry_eqn = (!G2L14 & G2L25) # (G2L14 & G2L26);
G2_safe_q[9]_lut_out = G2_safe_q[9] $ (!G2_cout & G2_safe_q[9]_carry_eqn);
G2_safe_q[9] = DFFEAS(G2_safe_q[9]_lut_out, GLOBAL(clk), GLOBAL(rd), , , , , , );

--G2L28 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT at LC_X12_Y6_N4
--operation mode is arithmetic

G2L28 = CARRY(!G2L26 # !G2_safe_q[9]);


--D1L231 is i2c:inst4|cnt_delay[19]~1137 at LC_X15_Y7_N3
--operation mode is normal

D1L231 = !D1L6 # !reset;


--D1_start_delaycnt is i2c:inst4|start_delaycnt at LC_X12_Y7_N2
--operation mode is normal

D1_start_delaycnt_lut_out = D1_main_state.00 & D1_start_delaycnt # !D1_main_state.00 & (D1L142 # D1_start_delaycnt & D1L6);
D1_start_delaycnt = DFFEAS(D1_start_delaycnt_lut_out, GLOBAL(clk), VCC, , , , , !reset, );


--D1L232 is i2c:inst4|cnt_delay[19]~1138 at LC_X12_Y7_N4
--operation mode is normal

D1L232 = D1_start_delaycnt # !reset;


--D1L15 is i2c:inst4|Equal~737 at LC_X5_Y7_N9
--operation mode is normal

D1L15 = !D1_clk_div[6] # !D1_clk_div[5] # !D1_clk_div[2];


--D1L174 is i2c:inst4|clk_div[7]~198 at LC_X5_Y7_N8
--operation mode is normal

D1L174 = !D1L15 & D1L8 & D1L12 # !reset;


--D1L286 is i2c:inst4|inner_state~925 at LC_X8_Y6_N8
--operation mode is normal

D1L286 = D1_i2c_state.write_data # D1_i2c_state.sendaddr # D1_i2c_state.read_data;


--D1L287 is i2c:inst4|inner_state~926 at LC_X9_Y5_N7
--operation mode is normal

D1L287 = D1_i2c_state.read_ini # !D1_i2c_state.ini;


--D1L288 is i2c:inst4|inner_state~927 at LC_X8_Y6_N2
--operation mode is normal

D1L288 = D1L286 # D1L287 & (!D1_phase3 # !D1_link);


--D1L289 is i2c:inst4|inner_state~928 at LC_X8_Y6_N3
--operation mode is normal

D1L289 = D1L49 # !D1_inner_state.start & D1L288 # !D1_main_state.10;


--D1L71 is i2c:inst4|Select~12590 at LC_X8_Y7_N1
--operation mode is normal

D1L71 = !D1_inner_state.start & (D1_i2c_state.ini # !D1_phase3 # !D1_link);


--D1L72 is i2c:inst4|Select~12591 at LC_X7_Y7_N9
--operation mode is normal

D1L72 = !D1_phase3 & (D1_inner_state.eighth # D1_inner_state.ack) # !D1L332;


--D1L73 is i2c:inst4|Select~12592 at LC_X7_Y7_N6
--operation mode is normal

D1L73 = D1_link & (D1L72 # D1_phase1 & !D1_inner_state.start) # !D1_link & D1_phase1 & !D1_inner_state.start;


--D1L291 is i2c:inst4|link~45 at LC_X7_Y7_N3
--operation mode is normal

D1L291 = D1_phase3 # D1_link;


--D1L74 is i2c:inst4|Select~12593 at LC_X7_Y7_N0
--operation mode is normal

D1L74 = D1_i2c_state.read_ini & (D1L73 # D1L291 & !D1L36);


--D1L75 is i2c:inst4|Select~12594 at LC_X7_Y7_N8
--operation mode is normal

D1L75 = D1_phase3 & (D1L332 & (!D1_inner_state.eighth) # !D1L332 & D1_link) # !D1_phase3 & D1_link;


--D1L76 is i2c:inst4|Select~12595 at LC_X7_Y7_N7
--operation mode is normal

D1L76 = D1L50 & (D1_i2c_state.read_data # D1_i2c_state.sendaddr & D1L75) # !D1L50 & D1_i2c_state.sendaddr & (D1L75);


--D1L77 is i2c:inst4|Select~12596 at LC_X7_Y7_N1
--operation mode is normal

D1L77 = D1L76 # D1L74 # D1_link & !D1L68;


--D1L78 is i2c:inst4|Select~12597 at LC_X8_Y7_N5
--operation mode is normal

D1L78 = D1_inner_state.stop # D1_inner_state.eighth & !D1_phase3 # !D1_inner_state.start;


--D1L79 is i2c:inst4|Select~12598 at LC_X8_Y7_N6
--operation mode is normal

D1L79 = D1_inner_state.start & (D1_link & D1L78) # !D1_inner_state.start & (D1_phase1 # D1_link & D1L78);


--D1L80 is i2c:inst4|Select~12599 at LC_X7_Y7_N5
--operation mode is normal

D1L80 = D1L79 # D1L291 & (D1_inner_state.ack # !D1L36);


--D1L81 is i2c:inst4|Select~12600 at LC_X7_Y7_N2
--operation mode is normal

D1L81 = D1L77 # !D1_i2c_state.ini & D1L80;


--D1L82 is i2c:inst4|Select~12601 at LC_X7_Y6_N7
--operation mode is normal

D1L82 = D1L62 & (D1L75 # D1L63) # !D1L62 & (D1_link & !D1L63);


--D1L83 is i2c:inst4|Select~12602 at LC_X7_Y6_N0
--operation mode is normal

D1L83 = D1L63 & (D1L82 & (D1L291) # !D1L82 & D1L80) # !D1L63 & D1L82;


--D1L84 is i2c:inst4|Select~12603 at LC_X7_Y6_N1
--operation mode is normal

D1L84 = D1L66 & D1_link & !D1_phase3 # !D1L66 & (D1L83);


--D1L85 is i2c:inst4|Select~12604 at LC_X9_Y8_N2
--operation mode is normal

D1L85 = D1_inner_state.sixth & (D1_inner_state.seventh # D1_phase3);


--D1L86 is i2c:inst4|Select~12605 at LC_X8_Y7_N8
--operation mode is normal

D1L86 = !D1_inner_state.stop & D1_inner_state.start & (D1_phase3);


--D1L87 is i2c:inst4|Select~12606 at LC_X6_Y8_N3
--operation mode is normal

D1L87 = D1L85 # !D1L86 & D1L59 & D1_inner_state.seventh;


--D1L88 is i2c:inst4|Select~12607 at LC_X6_Y8_N1
--operation mode is normal

D1L88 = !D1_phase3 & !D1_i2c_state.read_data & !D1_i2c_state.sendaddr;


--D1L89 is i2c:inst4|Select~12608 at LC_X6_Y8_N6
--operation mode is normal

D1L89 = D1_i2c_state.write_data & D1_inner_state.seventh # !D1_i2c_state.write_data & (D1L87 # D1_inner_state.seventh & D1L88);


--D1L90 is i2c:inst4|Select~12609 at LC_X9_Y6_N8
--operation mode is normal

D1L90 = D1_i2c_state.write_data # D1_i2c_state.sendaddr;


--D1L91 is i2c:inst4|Select~12610 at LC_X9_Y8_N0
--operation mode is normal

D1L91 = D1L90 & (D1L85 # D1_inner_state.seventh & !D1L86);


--D1L92 is i2c:inst4|Select~12611 at LC_X9_Y8_N9
--operation mode is normal

D1L92 = !D1_i2c_state.ini & D1_inner_state.sixth & (D1_phase3 # D1_inner_state.seventh);


--D1L93 is i2c:inst4|Select~12612 at LC_X9_Y6_N9
--operation mode is normal

D1L93 = D1_i2c_state.read_data # D1_i2c_state.read_ini # !D1_phase3 & !D1_i2c_state.ini;


--D1L94 is i2c:inst4|Select~12613 at LC_X9_Y8_N1
--operation mode is normal

D1L94 = D1L92 # D1L91 # D1_inner_state.seventh & D1L93;


--D1L95 is i2c:inst4|Select~12614 at LC_X7_Y8_N9
--operation mode is normal

D1L95 = D1_inner_state.fourth & (D1_inner_state.fifth # D1_phase3);


--D1L96 is i2c:inst4|Select~12615 at LC_X6_Y8_N8
--operation mode is normal

D1L96 = D1L95 # !D1L86 & D1_inner_state.fifth & D1L59;


--D1L97 is i2c:inst4|Select~12616 at LC_X6_Y8_N9
--operation mode is normal

D1L97 = D1_i2c_state.write_data & D1_inner_state.fifth # !D1_i2c_state.write_data & (D1L96 # D1_inner_state.fifth & D1L88);


--D1L98 is i2c:inst4|Select~12617 at LC_X9_Y8_N6
--operation mode is normal

D1L98 = D1_inner_state.fifth & (D1_inner_state.stop # !D1_inner_state.start # !D1_phase3);


--D1L99 is i2c:inst4|Select~12618 at LC_X9_Y8_N7
--operation mode is normal

D1L99 = D1L95 & (D1L90 # !D1_i2c_state.ini) # !D1L95 & D1L98 & (D1L90);


--D1L100 is i2c:inst4|Select~12619 at LC_X9_Y8_N8
--operation mode is normal

D1L100 = D1L99 # D1_inner_state.fifth & D1L93;


--D1L101 is i2c:inst4|Select~12620 at LC_X8_Y5_N2
--operation mode is normal

D1L101 = D1_inner_state.second & (D1_inner_state.third # D1_phase3);


--D1L102 is i2c:inst4|Select~12621 at LC_X8_Y5_N3
--operation mode is normal

D1L102 = D1L101 # D1_inner_state.third & D1L59 & !D1L86;


--D1L103 is i2c:inst4|Select~12622 at LC_X8_Y5_N4
--operation mode is normal

D1L103 = D1_i2c_state.write_data & D1_inner_state.third # !D1_i2c_state.write_data & (D1L102 # D1_inner_state.third & D1L88);


--D1L104 is i2c:inst4|Select~12623 at LC_X7_Y5_N9
--operation mode is normal

D1L104 = D1_inner_state.third & (D1_inner_state.stop # !D1_phase3 # !D1_inner_state.start);


--D1L105 is i2c:inst4|Select~12624 at LC_X7_Y5_N4
--operation mode is normal

D1L105 = D1L101 & (D1L90 # !D1_i2c_state.ini) # !D1L101 & (D1L104 & D1L90);


--D1L106 is i2c:inst4|Select~12625 at LC_X8_Y5_N7
--operation mode is normal

D1L106 = D1L105 # D1L93 & D1_inner_state.third;


--D1L107 is i2c:inst4|Select~12626 at LC_X9_Y5_N5
--operation mode is normal

D1L107 = D1L17 # D1_phase3 & (D1_inner_state.ack) # !D1_phase3 & D1_inner_state.first;


--D1L108 is i2c:inst4|Select~12627 at LC_X9_Y5_N9
--operation mode is normal

D1L108 = D1_inner_state.first & (D1L141 # D1L287 & D1L107) # !D1_inner_state.first & D1L287 & D1L107;


--D1L109 is i2c:inst4|Select~12628 at LC_X9_Y5_N6
--operation mode is normal

D1L109 = !D1_i2c_state.ini & D1L107;


--D1L110 is i2c:inst4|Select~12629 at LC_X9_Y5_N2
--operation mode is normal

D1L110 = D1L331 # !D1L86 & (D1_i2c_state.write_data # D1_i2c_state.sendaddr);


--D1L111 is i2c:inst4|Select~12630 at LC_X9_Y5_N3
--operation mode is normal

D1L111 = D1L49 # D1L109 # D1_inner_state.first & D1L110;


--D1L112 is i2c:inst4|Select~12631 at LC_X9_Y8_N4
--operation mode is normal

D1L112 = D1_inner_state.fifth & (D1_inner_state.sixth # D1_phase3);


--D1L113 is i2c:inst4|Select~12632 at LC_X10_Y8_N7
--operation mode is normal

D1L113 = D1L112 # !D1L86 & D1L59 & D1_inner_state.sixth;


--D1L114 is i2c:inst4|Select~12633 at LC_X10_Y8_N8
--operation mode is normal

D1L114 = D1_i2c_state.write_data & D1_inner_state.sixth # !D1_i2c_state.write_data & (D1L113 # D1_inner_state.sixth & D1L88);


--D1L115 is i2c:inst4|Select~12634 at LC_X9_Y8_N3
--operation mode is normal

D1L115 = D1_inner_state.sixth & (D1_inner_state.stop # !D1_inner_state.start # !D1_phase3);


--D1L116 is i2c:inst4|Select~12635 at LC_X9_Y8_N5
--operation mode is normal

D1L116 = D1L112 & (D1L90 # !D1_i2c_state.ini) # !D1L112 & D1L115 & (D1L90);


--D1L117 is i2c:inst4|Select~12636 at LC_X10_Y8_N5
--operation mode is normal

D1L117 = D1L116 # D1_inner_state.sixth & D1L93;


--D1L118 is i2c:inst4|Select~12637 at LC_X7_Y5_N0
--operation mode is normal

D1L118 = D1_inner_state.third & (D1_phase3 # D1_i