i2c_fpga.map.rpt

FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.

Info: Found 1 design units, including 1 entities, in source file i2c.v
    Info: Found entity 1: i2c
Info: Found 1 design units, including 1 entities, in source file i2c_test.v
    Info: Found entity 1: i2c_test
Info: Elaborating entity "I2C_FPGA" for the top level hierarchy
Warning: Processing legacy GDF or BDF entity "I2C_FPGA" with Max+Plus II bus and instance naming rules
Info: Elaborating entity "i2c" for hierarchy "i2c:inst4"
Warning (10230): Verilog HDL assignment warning at i2c.v(79): truncated value with size 32 to match size of target (20)
Warning (10230): Verilog HDL assignment warning at i2c.v(97): truncated value with size 32 to match size of target (8)
Info (10264): Verilog HDL Case Statement information at i2c.v(163): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(239): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(304): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(161): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(385): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(461): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(526): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(601): all case item expressions in this case statement are onehot
Info (10264): Verilog HDL Case Statement information at i2c.v(383): all case item expressions in this case statement are onehot
Warning (10230): Verilog HDL assignment warning at i2c.v(714): truncated value with size 32 to match size of target (12)
Info (10264): Verilog HDL Case Statement information at i2c.v(722): all case item expressions in this case statement are onehot
Warning (10270): Verilog HDL Case Statement warning at i2c.v(734): incomplete case statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at i2c.v(732): inferring latch(es) for variable "seg_data", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "seg_data[0]" at i2c.v(732)
Info (10041): Inferred latch for "seg_data[1]" at i2c.v(732)
Info (10041): Inferred latch for "seg_data[2]" at i2c.v(732)
Info (10041): Inferred latch for "seg_data[3]" at i2c.v(732)
Info (10041): Inferred latch for "seg_data[4]" at i2c.v(732)
Info (10041): Inferred latch for "seg_data[5]" at i2c.v(732)
Info (10041): Inferred latch for "seg_data[6]" at i2c.v(732)
Info (10041): Inferred latch for "seg_data[7]" at i2c.v(732)
Info: Elaborating entity "i2c_test" for hierarchy "i2c_test:inst1"
Warning: Using design file delay_reset_block.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: delay_reset_block
Info: Elaborating entity "delay_reset_block" for hierarchy "delay_reset_block:inst2"
Warning: Processing legacy GDF or BDF entity "delay_reset_block" with Max+Plus II bus and instance naming rules
Warning: Using design file reset_counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: reset_counter
Info: Elaborating entity "reset_counter" for hierarchy "delay_reset_block:inst2|reset_counter:inst"
Info: Found 1 design units, including 1 entities, in source file ../../../../../programfile/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Elaborating entity "lpm_counter" for hierarchy "delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component"
Info: Elaborated megafunction instantiation "delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component"
Info: Found 1 design units, including 1 entities, in source file db/cntr_p7j.tdf
    Info: Found entity 1: cntr_p7j
Info: Elaborating entity "cntr_p7j" for hierarchy "delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_p7j:auto_generated"
Warning (14130): Reduced register "i2c:inst4|addr[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "i2c:inst4|addr[6]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "i2c:inst4|addr[5]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "i2c:inst4|addr[4]" with stuck data_in port to stuck value GND
Info: Power-up level of register "i2c:inst4|addr[3]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "i2c:inst4|addr[3]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "i2c:inst4|addr[2]" with stuck data_in port to stuck value GND
Info: Power-up level of register "i2c:inst4|addr[1]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "i2c:inst4|addr[1]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "i2c:inst4|addr[0]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "i2c:inst4|writeData_reg[6]" merged to single register "i2c:inst4|writeData_reg[4]"
    Info: Duplicate register "i2c:inst4|writeData_reg[7]" merged to single register "i2c:inst4|writeData_reg[4]"
    Info: Duplicate register "i2c:inst4|writeData_reg[5]" merged to single register "i2c:inst4|writeData_reg[4]"
Warning (14130): Reduced register "i2c:inst4|writeData_reg[4]" with stuck data_in port to stuck value GND
Info: State machine "|I2C_FPGA|i2c:inst4|inner_state" contains 11 states
Info: State machine "|I2C_FPGA|i2c:inst4|i2c_state" contains 5 states
Info: State machine "|I2C_FPGA|i2c:inst4|main_state" contains 3 states
Info: Selected Auto state machine encoding method for state machine "|I2C_FPGA|i2c:inst4|inner_state"
Info: Encoding result for state machine "|I2C_FPGA|i2c:inst4|inner_state"
    Info: Completed encoding using 11 state bits
        Info: Encoded state bit "i2c:inst4|inner_state.stop"
        Info: Encoded state bit "i2c:inst4|inner_state.ack"
        Info: Encoded state bit "i2c:inst4|inner_state.eighth"
        Info: Encoded state bit "i2c:inst4|inner_state.seventh"
        Info: Encoded state bit "i2c:inst4|inner_state.sixth"
        Info: Encoded state bit "i2c:inst4|inner_state.fifth"
        Info: Encoded state bit "i2c:inst4|inner_state.fourth"
        Info: Encoded state bit "i2c:inst4|inner_state.third"
        Info: Encoded state bit "i2c:inst4|inner_state.second"
        Info: Encoded state bit "i2c:inst4|inner_state.first"
        Info: Encoded state bit "i2c:inst4|inner_state.start"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.start" uses code string "00000000000"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.first" uses code string "00000000011"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.second" uses code string "00000000101"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.third" uses code string "00000001001"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.fourth" uses code string "00000010001"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.fifth" uses code string "00000100001"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.sixth" uses code string "00001000001"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.seventh" uses code string "00010000001"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.eighth" uses code string "00100000001"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.ack" uses code string "01000000001"
    Info: State "|I2C_FPGA|i2c:inst4|inner_state.stop" uses code string "10000000001"
Info: Selected Auto state machine encoding method for state machine "|I2C_FPGA|i2c:inst4|i2c_state"
Info: Encoding result for state machine "|I2C_FPGA|i2c:inst4|i2c_state"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "i2c:inst4|i2c_state.read_data"
        Info: Encoded state bit "i2c:inst4|i2c_state.write_data"
        Info: Encoded state bit "i2c:inst4|i2c_state.sendaddr"
        Info: Encoded state bit "i2c:inst4|i2c_state.ini"
        Info: Encoded state bit "i2c:inst4|i2c_state.read_ini"
    Info: State "|I2C_FPGA|i2c:inst4|i2c_state.ini" uses code string "00000"
    Info: State "|I2C_FPGA|i2c:inst4|i2c_state.sendaddr" uses code string "00110"
    Info: State "|I2C_FPGA|i2c:inst4|i2c_state.write_data" uses code string "01010"
    Info: State "|I2C_FPGA|i2c:inst4|i2c_state.read_data" uses code string "10010"
    Info: State "|I2C_FPGA|i2c:inst4|i2c_state.read_ini" uses code string "00011"
Info: Selected Auto state machine encoding method for state machine "|I2C_FPGA|i2c:inst4|main_state"
Info: Encoding result for state machine "|I2C_FPGA|i2c:inst4|main_state"
    Info: Completed encoding using 3 state bits
        Info: Encoded state bit "i2c:inst4|main_state.00"
        Info: Encoded state bit "i2c:inst4|main_state.10"
        Info: Encoded state bit "i2c:inst4|main_state.01"
    Info: State "|I2C_FPGA|i2c:inst4|main_state.00" uses code string "000"
    Info: State "|I2C_FPGA|i2c:inst4|main_state.01" uses code string "101"
    Info: State "|I2C_FPGA|i2c:inst4|main_state.10" uses code string "110"
Warning: Latch i2c:inst4|seg_data[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4|en[1]
Warning: Latch i2c:inst4|seg_data[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4|en[1]
Warning: Latch i2c:inst4|seg_data[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4|en[1]
Warning: Latch i2c:inst4|seg_data[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4|en[1]
Warning: Latch i2c:inst4|seg_data[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4|en[1]
Warning: Latch i2c:inst4|seg_data[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4|en[1]
Warning: Latch i2c:inst4|seg_data[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal i2c:inst4|en[1]
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "seg_data[7]" stuck at VCC
Info: 6 registers lost all their fanouts during netlist optimizations. The first 6 are displayed below.
    Info: Register "i2c:inst4|inner_state~162" lost all its fanouts during netlist optimizations.
    Info: Register "i2c:inst4|inner_state~163" lost all its fanouts during netlist optimizations.
    Info: Register "i2c:inst4|inner_state~164" lost all its fanouts during netlist optimizations.
    Info: Register "i2c:inst4|inner_state~165" lost all its fanouts during netlist optimizations.
    Info: Register "i2c:inst4|i2c_state~74" lost all its fanouts during netlist optimizations.
    Info: Register "i2c:inst4|i2c_state~75" lost all its fanouts during netlist optimizations.
Info: Implemented 291 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 11 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 275 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 34 warnings
    Info: Allocated 150 megabytes of memory during processing
    Info: Processing ended: Thu May 29 16:15:40 2008
    Info: Elapsed time: 00:00:12