i2c_fpga.tan.rpt

FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.

; Clock Hold: 'clk'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                                            ; i2c:inst4|readData_reg[3]   ; i2c:inst4|seg_data[2]     ; clk        ; clk      ; 77           ;
; Total number of failed paths ;                                          ;               ;                                                ;                             ;                           ;            ;          ; 77           ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------------------+---------------------------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C5Q208C8        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; write           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                         ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                           ; To                            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------------------------------------------------------------------+-------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 107.56 MHz ( period = 9.297 ns )                    ; i2c:inst4|inner_state.fifth                                                                                    ; i2c:inst4|sda_buf             ; clk        ; clk      ; None                        ; None                      ; 9.022 ns                ;
; N/A                                     ; 109.46 MHz ( period = 9.136 ns )                    ; i2c:inst4|inner_state.third                                                                                    ; i2c:inst4|sda_buf             ; clk        ; clk      ; None                        ; None                      ; 8.861 ns                ;
; N/A                                     ; 110.66 MHz ( period = 9.037 ns )                    ; i2c:inst4|phase0                                                                                               ; i2c:inst4|sda_buf             ; clk        ; clk      ; None                        ; None                      ; 8.752 ns                ;