i2c_fpga.map.eqn

FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.

--D1L53 is i2c:inst4|Select~12572
--operation mode is normal

D1L53 = D1L52 & !D1_phase1 & (D1_inner_state.stop # D1_phase3);


--C1_inst4 is delay_reset_block:inst2|inst4
--operation mode is normal

C1_inst4 = !write # !G1_cout;


--D1L273 is i2c:inst4|main_state~2373
--operation mode is normal

D1L273 = !D1_phase3 # !D1_inner_state.stop;


--D1L274 is i2c:inst4|main_state~2374
--operation mode is normal

D1L274 = D1_i2c_state.read_data & D1L273 # !D1_i2c_state.read_data & (!D1_sda_buf # !D1_phase1);


--D1L275 is i2c:inst4|main_state~2375
--operation mode is normal

D1L275 = D1_main_state.10 & (D1L274 # !D1_i2c_state.read_data & !D1L267);


--D1L276 is i2c:inst4|main_state~2376
--operation mode is normal

D1L276 = D1L271 & (!D1_main_state.00 & !D1L6);


--D1L54 is i2c:inst4|Select~12573
--operation mode is normal

D1L54 = D1_inner_state.ack & D1_i2c_state.read_ini & D1_phase3;


--D1L277 is i2c:inst4|main_state~2378
--operation mode is normal

D1L277 = D1_i2c_state.write_data & (D1_inner_state.stop & D1_phase3 # !D1_inner_state.stop & (D1_sda_buf)) # !D1_i2c_state.write_data & (D1_sda_buf);


--D1L278 is i2c:inst4|main_state~2379
--operation mode is normal

D1L278 = D1_inner_state.ack & D1_phase1 & !D1_i2c_state.read_ini & !D1_i2c_state.read_data;


--D1L279 is i2c:inst4|main_state~2380
--operation mode is normal

D1L279 = D1_i2c_state.write_data & D1_phase3 & !D1_inner_state.ack;


--D1L280 is i2c:inst4|main_state~2381
--operation mode is normal

D1L280 = D1_main_state.01 & !D1L283 & (!D1L278 # !D1L277);


--D1L55 is i2c:inst4|Select~12574
--operation mode is normal

D1L55 = D1_inner_state.ack & D1_phase3 & !D1_i2c_state.read_data & !D1_i2c_state.write_data;


--D1L56 is i2c:inst4|Select~12575
--operation mode is normal

D1L56 = D1L49 # D1_i2c_state.read_ini & (!D1L55);


--D1L300 is i2c:inst4|reduce_nor~89
--operation mode is normal

D1L300 = D1_inner_state.start & (!D1_inner_state.stop);


--D1L57 is i2c:inst4|Select~12576
--operation mode is normal

D1L57 = D1_phase3 & (D1L300 & D1_inner_state.eighth # !D1L300 & (D1_inner_state.ack)) # !D1_phase3 & (D1_inner_state.ack);


--D1L58 is i2c:inst4|Select~12577
--operation mode is normal

D1L58 = D1_phase3 & D1_inner_state.eighth # !D1_phase3 & (D1_inner_state.ack);


--D1L59 is i2c:inst4|Select~12578
--operation mode is normal

D1L59 = D1_i2c_state.read_data # D1_i2c_state.sendaddr;


--D1L60 is i2c:inst4|Select~12579
--operation mode is normal

D1L60 = D1_i2c_state.write_data & D1_inner_state.ack # !D1_i2c_state.write_data & (D1L140);


--D1L61 is i2c:inst4|Select~12580
--operation mode is normal

D1L61 = D1_inner_state.eighth # D1L300 & (!D1_phase1 # !D1_inner_state.ack);


--D1L62 is i2c:inst4|Select~12581
--operation mode is normal

D1L62 = D1_i2c_state.sendaddr # D1_i2c_state.write_data & D1L61;


--D1L63 is i2c:inst4|Select~12582
--operation mode is normal

D1L63 = D1_i2c_state.write_data & (D1L61 # !D1_i2c_state.sendaddr & !D1_i2c_state.ini) # !D1_i2c_state.write_data & (!D1_i2c_state.sendaddr & !D1_i2c_state.ini);


--D1L64 is i2c:inst4|Select~12583
--operation mode is normal

D1L64 = D1L62 & (D1L63) # !D1L62 & (D1L63 & D1L58 # !D1L63 & (D1_inner_state.ack));


--D1L253 is i2c:inst4|inner_state~924
--operation mode is normal

D1L253 = D1_inner_state.ack & (!D1_phase3);


--D1L65 is i2c:inst4|Select~12584
--operation mode is normal

D1L65 = D1L62 & (D1L64 & (D1L253) # !D1L64 & D1L57) # !D1L62 & (D1L64);


--D1L66 is i2c:inst4|Select~12585
--operation mode is normal

D1L66 = D1_i2c_state.write_data & D1_inner_state.eighth;


--D1L67 is i2c:inst4|Select~12586
--operation mode is normal

D1L67 = D1L66 & (D1_inner_state.ack # D1_phase3) # !D1L66 & D1L65;


--D1L68 is i2c:inst4|Select~12587
--operation mode is normal

D1L68 = !D1_i2c_state.read_data & !D1_i2c_state.write_data;


--D1L69 is i2c:inst4|Select~12588
--operation mode is normal

D1L69 = D1L50 & (D1_i2c_state.sendaddr & !D1L68 # !D1_i2c_state.ini) # !D1L50 & D1_i2c_state.sendaddr;


--D1L70 is i2c:inst4|Select~12589
--operation mode is normal

D1L70 = D1_inner_state.ack & (D1_phase3 & (!D1_i2c_state.ini) # !D1_phase3 & D1_i2c_state.sendaddr) # !D1_inner_state.ack & D1_i2c_state.sendaddr;


--D1L241 is i2c:inst4|i2c_state~243
--operation mode is normal

D1L241 = !D1_i2c_state.ini & (D1_i2c_state.read_ini & !D1_main_state.10 # !D1L55);


--D1L14 is i2c:inst4|Equal~736
--operation mode is normal

D1L14 = D1L8 & D1L12 & D1L13 & !D1_clk_div[6];


--G1_safe_q[9] is delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[9]
--operation mode is arithmetic

G1_safe_q[9]_carry_eqn = G1L18;
G1_safe_q[9]_lut_out = G1_safe_q[9] $ (!G1_cout & G1_safe_q[9]_carry_eqn);
G1_safe_q[9] = DFFEAS(G1_safe_q[9]_lut_out, clk, write, , , , , , );

--G1L20 is delay_reset_block:inst2|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT
--operation mode is arithmetic

G1L20 = CARRY(!G1L18 # !G1_safe_q[9]);


--G2_safe_q[9] is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|safe_q[9]
--operation mode is arithmetic

G2_safe_q[9]_carry_eqn = G2L18;
G2_safe_q[9]_lut_out = G2_safe_q[9] $ (!G2_cout & G2_safe_q[9]_carry_eqn);
G2_safe_q[9] = DFFEAS(G2_safe_q[9]_lut_out, clk, rd, , , , , , );

--G2L20 is delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_1ub:auto_generated|counter_cella9~COUT
--operation mode is arithmetic

G2L20 = CARRY(!G2L18 # !G2_safe_q[9]);


--D1L207 is i2c:inst4|cnt_delay[19]~1137
--operation mode is normal

D1L207 = !D1L6 # !reset;


--D1_start_delaycnt is i2c:inst4|start_delaycnt
--operation mode is normal

D1_start_delaycnt_lut_out = D1_main_state.00 & D1_start_delaycnt # !D1_main_state.00 & (D1L142 # D1_start_delaycnt & D1L6);
D1_start_delaycnt = DFFEAS(D1_start_delaycnt_lut_out, clk, VCC, , , , , !reset, );


--D1L208 is i2c:inst4|cnt_delay[19]~1138
--operation mode is normal

D1L208 = D1_start_delaycnt # !reset;


--D1L15 is i2c:inst4|Equal~737
--operation mode is normal

D1L15 = !D1_clk_div[6] # !D1_clk_div[5] # !D1_clk_div[2];


--D1L166 is i2c:inst4|clk_div[7]~198
--operation mode is normal

D1L166 = !D1L15 & D1L8 & D1L12 # !reset;


--D1L254 is i2c:inst4|inner_state~925
--operation mode is normal

D1L254 = D1_i2c_state.read_data # D1_i2c_state.write_data # D1_i2c_state.sendaddr;


--D1L255 is i2c:inst4|inner_state~926
--operation mode is normal

D1L255 = D1_i2c_state.read_ini # !D1_i2c_state.ini;


--D1L256 is i2c:inst4|inner_state~927
--operation mode is normal

D1L256 = D1L254 # D1L255 & (!D1_link # !D1_phase3);


--D1L257 is i2c:inst4|inner_state~928
--operation mode is normal

D1L257 = D1L49 # D1L256 & !D1_inner_state.start # !D1_main_state.10;


--D1L71 is i2c:inst4|Select~12590
--operation mode is normal

D1L71 = !D1_inner_state.start & (D1_i2c_state.ini # !D1_link # !D1_phase3);


--D1L72 is i2c:inst4|Select~12591
--operation mode is normal

D1L72 = !D1_phase3 & (D1_inner_state.ack # D1_inner_state.eighth) # !D1L300;


--D1L73 is i2c:inst4|Select~12592
--operation mode is normal

D1L73 = D1_link & (D1L72 # D1_phase1 & !D1_inner_state.start) # !D1_link & (D1_phase1 & !D1_inner_state.start);


--D1L259 is i2c:inst4|link~45
--operation mode is normal

D1L259 = D1_phase3 # D1_link;


--D1L74 is i2c:inst4|Select~12593
--operation mode is normal

D1L74 = D1_i2c_state.read_ini & (D1L73 # D1L259 & !D1L36);


--D1L75 is i2c:inst4|Select~12594
--operation mode is normal

D1L75 = D1_phase3 & (D1L300 & (!D1_inner_state.eighth) # !D1L300 & D1_link) # !D1_phase3 & D1_link;


--D1L76 is i2c:inst4|Select~12595
--operation mode is normal

D1L76 = D1_i2c_state.read_data & (D1L50 # D1_i2c_state.sendaddr & D1L75) # !D1_i2c_state.read_data & D1_i2c_state.sendaddr & D1L75;


--D1L77 is i2c:inst4|Select~12596
--operation mode is normal

D1L77 = D1L74 # D1L76 # D1_link & !D1L68;


--D1L78 is i2c:inst4|Select~12597
--operation mode is normal

D1L78 = D1_inner_state.stop # D1_inner_state.eighth & !D1_phase3 # !D1_inner_state.start;


--D1L79 is i2c:inst4|Select~12598
--operation mode is normal

D1L79 = D1_link & (D1L78 # D1_phase1 & !D1_inner_state.start) # !D1_link & (D1_phase1 & !D1_inner_state.start);


--D1L80 is i2c:inst4|Select~12599
--operation mode is normal

D1L80 = D1L79 # D1L259 & (D1_inner_state.ack # !D1L36);


--D1L81 is i2c:inst4|Select~12600
--operation mode is normal

D1L81 = D1L77 # D1L80 & (!D1_i2c_state.ini);


--D1L82 is i2c:inst4|Select~12601
--operation mode is normal

D1L82 = D1L63 & (D1L62) # !D1L63 & (D1L62 & D1L75 # !D1L62 & (D1_link));


--D1L83 is i2c:inst4|Select~12602
--operation mode is normal

D1L83 = D1L63 & (D1L82 & (D1L259) # !D1L82 & D1L80) # !D1L63 & (D1L82);


--D1L84 is i2c:inst4|Select~12603
--operation mode is normal

D1L84 = D1L66 & (D1_link & !D1_phase3) # !D1L66 & D1L83;


--D1L85 is i2c:inst4|Select~12604
--operation mode is normal

D1L85 = D1_inner_state.sixth & (D1_phase3 # D1_inner_state.seventh);


--D1L86 is i2c:inst4|Select~12605
--operation mode is normal

D1L86 = D1_phase3 & D1_inner_state.start & (!D1_inner_state.stop);


--D1L87 is i2c:inst4|Select~12606
--operation mode is normal

D1L87 = D1L85 # D1_inner_state.seventh & D1L59 & !D1L86;


--D1L88 is i2c:inst4|Select~12607
--operation mode is normal

D1L88 = !D1_i2c_state.read_data & !D1_i2c_state.sendaddr & !D1_phase3;


--D1L89 is i2c:inst4|Select~12608
--operation mode is normal

D1L89 = D1_i2c_state.write_data & D1_inner_state.seventh # !D1_i2c_state.write_data & (D1L87 # D1_inner_state.seventh & D1L88);


--D1L90 is i2c:inst4|Select~12609
--operation mode is normal

D1L90 = D1_i2c_state.write_data # D1_i2c_state.sendaddr;


--D1L91 is i2c:inst4|Select~12610
--operation mode is normal

D1L91 = D1L90 & (D1L85 # D1_inner_state.seventh & !D1L86);


--D1L92 is i2c:inst4|Select~12611
--operation mode is normal

D1L92 = D1_inner_state.sixth & !D1_i2c_state.ini & (D1_phase3 # D1_inner_state.seventh);


--D1L93 is i2c:inst4|Select~12612
--operation mode is normal

D1L93 = D1_i2c_state.read_ini # D1_i2c_state.read_data # !D1_phase3 & !D1_i2c_state.ini;


--D1L94 is i2c:inst4|Select~12613
--operation mode is normal

D1L94 = D1L91 # D1L92 # D1_inner_state.seventh & D1L93;


--D1L95 is i2c:inst4|Select~12614
--operation mode is normal

D1L95 = D1_inner_state.fourth & (D1_phase3 # D1_inner_state.fifth);


--D1L96 is i2c:inst4|Select~12615
--operation mode is normal

D1L96 = D1L95 # D1_inner_state.fifth & D1L59 & !D1L86;


--D1L97 is i2c:inst4|Select~12616
--operation mode is normal

D1L97 = D1_i2c_state.write_data & D1_inner_state.fifth # !D1_i2c_state.write_data & (D1L96 # D1_inner_state.fifth & D1L88);


--D1L98 is i2c:inst4|Select~12617
--operation mode is normal

D1L98 = D1_inner_state.fifth & (D1_inner_state.stop # !D1_inner_state.start # !D1_phase3);


--D1L99 is i2c:inst4|Select~12618
--operation mode is normal

D1L99 = D1L90 & (D1L95 # D1L98) # !D1L90 & D1L95 & (!D1_i2c_state.ini);