i2c_fpga.map.eqn

FPGA EP2C5Q288C8 I2C 原码,测试OK 打开即用.

--D1_clk_div[3] is i2c:inst4|clk_div[3]
--operation mode is arithmetic

D1_clk_div[3]_carry_eqn = D1L156;
D1_clk_div[3]_lut_out = D1_clk_div[3] $ (D1_clk_div[3]_carry_eqn);
D1_clk_div[3] = DFFEAS(D1_clk_div[3]_lut_out, clk, VCC, , , , , D1L166, );

--D1L158 is i2c:inst4|clk_div[3]~179
--operation mode is arithmetic

D1L158 = CARRY(!D1L156 # !D1_clk_div[3]);


--D1L7 is i2c:inst4|Equal~729
--operation mode is normal

D1L7 = D1_clk_div[0] & D1_clk_div[5] & !D1_clk_div[2] & !D1_clk_div[3];


--D1_clk_div[4] is i2c:inst4|clk_div[4]
--operation mode is arithmetic

D1_clk_div[4]_carry_eqn = D1L158;
D1_clk_div[4]_lut_out = D1_clk_div[4] $ (!D1_clk_div[4]_carry_eqn);
D1_clk_div[4] = DFFEAS(D1_clk_div[4]_lut_out, clk, VCC, , , , , D1L166, );

--D1L160 is i2c:inst4|clk_div[4]~183
--operation mode is arithmetic

D1L160 = CARRY(D1_clk_div[4] & (!D1L158));


--D1_clk_div[1] is i2c:inst4|clk_div[1]
--operation mode is arithmetic

D1_clk_div[1]_carry_eqn = D1L152;
D1_clk_div[1]_lut_out = D1_clk_div[1] $ (D1_clk_div[1]_carry_eqn);
D1_clk_div[1] = DFFEAS(D1_clk_div[1]_lut_out, clk, VCC, , , , , D1L166, );

--D1L154 is i2c:inst4|clk_div[1]~187
--operation mode is arithmetic

D1L154 = CARRY(!D1L152 # !D1_clk_div[1]);


--D1L8 is i2c:inst4|Equal~730
--operation mode is normal

D1L8 = D1_clk_div[4] & (!D1_clk_div[1]);


--D1_clk_div[7] is i2c:inst4|clk_div[7]
--operation mode is normal

D1_clk_div[7]_carry_eqn = D1L164;
D1_clk_div[7]_lut_out = D1_clk_div[7] $ (D1_clk_div[7]_carry_eqn);
D1_clk_div[7] = DFFEAS(D1_clk_div[7]_lut_out, clk, VCC, , , , , D1L166, );


--D1_clk_div[6] is i2c:inst4|clk_div[6]
--operation mode is arithmetic

D1_clk_div[6]_carry_eqn = D1L162;
D1_clk_div[6]_lut_out = D1_clk_div[6] $ (!D1_clk_div[6]_carry_eqn);
D1_clk_div[6] = DFFEAS(D1_clk_div[6]_lut_out, clk, VCC, , , , , D1L166, );

--D1L164 is i2c:inst4|clk_div[6]~195
--operation mode is arithmetic

D1L164 = CARRY(D1_clk_div[6] & (!D1L162));


--D1L9 is i2c:inst4|Equal~731
--operation mode is normal

D1L9 = D1L7 & D1L8 & !D1_clk_div[7] & !D1_clk_div[6];


--D1L10 is i2c:inst4|Equal~732
--operation mode is normal

D1L10 = D1_clk_div[6] & D1_clk_div[1] & (!D1_clk_div[4]);


--D1L11 is i2c:inst4|Equal~733
--operation mode is normal

D1L11 = D1L7 & D1L10 & (!D1_clk_div[7]);


--B1_counter[0] is i2c_test:inst1|counter[0]
--operation mode is normal

B1_counter[0]_lut_out = !B1_counter[0];
B1_counter[0] = DFFEAS(B1_counter[0]_lut_out, C1_inst4, reset, , , , , , );


--D1L330 is i2c:inst4|writeData_reg[0]~782
--operation mode is normal

D1L330 = !reset # !D1_main_state.00;


--D1_inner_state.start is i2c:inst4|inner_state.start
--operation mode is normal

D1_inner_state.start_lut_out = reset & (!D1L71 & D1_main_state.01 # !D1L257);
D1_inner_state.start = DFFEAS(D1_inner_state.start_lut_out, clk, VCC, , , , , , );


--D1L295 is i2c:inst4|readData_reg[5]~616
--operation mode is normal

D1L295 = D1_inner_state.stop # !D1_inner_state.start # !D1_main_state.10 # !D1_i2c_state.read_data;


--D1L296 is i2c:inst4|readData_reg[5]~617
--operation mode is normal

D1L296 = !D1_inner_state.ack & !D1L295 & D1_phase1 # !reset;


--B1_counter[1] is i2c_test:inst1|counter[1]
--operation mode is normal

B1_counter[1]_lut_out = B1_counter[0] $ B1_counter[1];
B1_counter[1] = DFFEAS(B1_counter[1]_lut_out, C1_inst4, reset, , , , , , );


--B1_counter[2] is i2c_test:inst1|counter[2]
--operation mode is normal

B1_counter[2]_lut_out = B1_counter[2] $ (B1_counter[0] & B1_counter[1]);
B1_counter[2] = DFFEAS(B1_counter[2]_lut_out, C1_inst4, reset, , , , , , );


--B1_counter[3] is i2c_test:inst1|counter[3]
--operation mode is normal

B1_counter[3]_lut_out = B1_counter[3] $ (B1_counter[0] & B1_counter[1] & B1_counter[2]);
B1_counter[3] = DFFEAS(B1_counter[3]_lut_out, C1_inst4, reset, , , , , , );


--D1_link is i2c:inst4|link
--operation mode is normal

D1_link_lut_out = D1_main_state.10 & (D1L81 # D1_main_state.01 & D1L84) # !D1_main_state.10 & (D1_main_state.01 & D1L84);
D1_link = DFFEAS(D1_link_lut_out, clk, VCC, , , , , !reset, );


--D1L17 is i2c:inst4|Select~12536
--operation mode is normal

D1L17 = D1_phase3 & D1_link & (!D1_inner_state.start);


--D1L18 is i2c:inst4|Select~12537
--operation mode is normal

D1L18 = D1_inner_state.ack & (D1_phase0 & A1L6 # !D1_phase0 & (D1_sda_buf));


--D1_inner_state.seventh is i2c:inst4|inner_state.seventh
--operation mode is normal

D1_inner_state.seventh_lut_out = D1_main_state.10 & (D1L89 # D1_main_state.01 & D1L94) # !D1_main_state.10 & (D1_main_state.01 & D1L94);
D1_inner_state.seventh = DFFEAS(D1_inner_state.seventh_lut_out, clk, VCC, , , , , !reset, );


--D1_inner_state.fifth is i2c:inst4|inner_state.fifth
--operation mode is normal

D1_inner_state.fifth_lut_out = D1_main_state.10 & (D1L97 # D1_main_state.01 & D1L100) # !D1_main_state.10 & (D1_main_state.01 & D1L100);
D1_inner_state.fifth = DFFEAS(D1_inner_state.fifth_lut_out, clk, VCC, , , , , !reset, );


--D1_inner_state.third is i2c:inst4|inner_state.third
--operation mode is normal

D1_inner_state.third_lut_out = D1_main_state.10 & (D1L103 # D1_main_state.01 & D1L106) # !D1_main_state.10 & (D1_main_state.01 & D1L106);
D1_inner_state.third = DFFEAS(D1_inner_state.third_lut_out, clk, VCC, , , , , !reset, );


--D1_inner_state.first is i2c:inst4|inner_state.first
--operation mode is normal

D1_inner_state.first_lut_out = D1_main_state.10 & (D1L108 # D1_main_state.01 & D1L111) # !D1_main_state.10 & (D1_main_state.01 & D1L111);
D1_inner_state.first = DFFEAS(D1_inner_state.first_lut_out, clk, VCC, , , , , !reset, );


--D1L19 is i2c:inst4|Select~12538
--operation mode is normal

D1L19 = !D1_inner_state.fifth & !D1_inner_state.third & !D1_inner_state.first;


--D1_inner_state.sixth is i2c:inst4|inner_state.sixth
--operation mode is normal

D1_inner_state.sixth_lut_out = D1_main_state.10 & (D1L114 # D1_main_state.01 & D1L117) # !D1_main_state.10 & (D1_main_state.01 & D1L117);
D1_inner_state.sixth = DFFEAS(D1_inner_state.sixth_lut_out, clk, VCC, , , , , !reset, );


--D1_inner_state.fourth is i2c:inst4|inner_state.fourth
--operation mode is normal

D1_inner_state.fourth_lut_out = D1_main_state.10 & (D1L120 # D1_main_state.01 & D1L123) # !D1_main_state.10 & (D1_main_state.01 & D1L123);
D1_inner_state.fourth = DFFEAS(D1_inner_state.fourth_lut_out, clk, VCC, , , , , !reset, );


--D1L20 is i2c:inst4|Select~12539
--operation mode is normal

D1L20 = !D1_inner_state.sixth & !D1_inner_state.fourth;


--D1_inner_state.second is i2c:inst4|inner_state.second
--operation mode is normal

D1_inner_state.second_lut_out = D1_main_state.10 & (D1L126 # D1_main_state.01 & D1L129) # !D1_main_state.10 & (D1_main_state.01 & D1L129);
D1_inner_state.second = DFFEAS(D1_inner_state.second_lut_out, clk, VCC, , , , , !reset, );


--D1_inner_state.eighth is i2c:inst4|inner_state.eighth
--operation mode is normal

D1_inner_state.eighth_lut_out = D1_main_state.10 & (D1L132 # D1_main_state.01 & D1L135) # !D1_main_state.10 & (D1_main_state.01 & D1L135);
D1_inner_state.eighth = DFFEAS(D1_inner_state.eighth_lut_out, clk, VCC, , , , , !reset, );


--D1L21 is i2c:inst4|Select~12540
--operation mode is normal

D1L21 = D1_inner_state.stop # D1_inner_state.eighth # !D1_phase1 & !D1_inner_state.start;


--D1L22 is i2c:inst4|Select~12541
--operation mode is normal

D1L22 = D1_inner_state.second # D1_sda_buf & D1L21;


--D1L23 is i2c:inst4|Select~12542
--operation mode is normal

D1L23 = D1_phase3 & (D1L22) # !D1_phase3 & D1_sda_buf & (D1L22 # !D1L137);


--D1L24 is i2c:inst4|Select~12543
--operation mode is normal

D1L24 = !D1_i2c_state.ini & (D1L136 # D1L23);


--D1L25 is i2c:inst4|Select~12544
--operation mode is normal

D1L25 = D1_sda_buf & (D1_i2c_state.read_ini # D1_i2c_state.read_data) # !D1_main_state.01;


--D1L26 is i2c:inst4|Select~12545
--operation mode is normal

D1L26 = D1L18 & (!D1_phase3);


--D1L27 is i2c:inst4|Select~12546
--operation mode is normal

D1L27 = !D1_inner_state.seventh & !D1_inner_state.second & D1L19;


--D1L28 is i2c:inst4|Select~12547
--operation mode is normal

D1L28 = !D1_inner_state.stop & !D1_inner_state.eighth & D1_inner_state.start;


--D1L29 is i2c:inst4|Select~12548
--operation mode is normal

D1L29 = D1_phase3 & (D1L138) # !D1_phase3 & (D1L27 & D1L138 # !D1_sda_buf);


--D1L30 is i2c:inst4|Select~12549
--operation mode is normal

D1L30 = D1L25 # D1_i2c_state.sendaddr & (D1L26 # !D1L29);


--D1L31 is i2c:inst4|Select~12550
--operation mode is normal

D1L31 = D1_sda_buf & (D1_inner_state.stop # D1_inner_state.eighth # !D1_inner_state.start);


--D1L32 is i2c:inst4|Select~12551
--operation mode is normal

D1L32 = D1_inner_state.sixth & (D1_writeData_reg[1] # D1_inner_state.fourth & D1_writeData_reg[3]) # !D1_inner_state.sixth & D1_inner_state.fourth & D1_writeData_reg[3];


--D1L33 is i2c:inst4|Select~12552
--operation mode is normal

D1L33 = D1_inner_state.seventh & (D1_writeData_reg[0] # D1_inner_state.fifth & D1_writeData_reg[2]) # !D1_inner_state.seventh & D1_inner_state.fifth & D1_writeData_reg[2];


--D1L34 is i2c:inst4|Select~12553
--operation mode is normal

D1L34 = D1L31 # D1_phase3 & (D1L32 # D1L33);


--D1L35 is i2c:inst4|Select~12554
--operation mode is normal

D1L35 = D1_phase1 & (D1L18 # D1_inner_state.stop) # !D1_phase1 & D1L18 & (!D1_phase3);


--D1L313 is i2c:inst4|sda_buf~139
--operation mode is normal

D1L313 = D1_sda_buf & (!D1_phase3);


--D1L36 is i2c:inst4|Select~12555
--operation mode is normal

D1L36 = D1L19 & D1L20 & !D1_inner_state.seventh & !D1_inner_state.second;


--D1L37 is i2c:inst4|Select~12556
--operation mode is normal

D1L37 = D1L34 # D1L35 # D1L313 & !D1L36;


--D1L38 is i2c:inst4|Select~12557
--operation mode is normal

D1L38 = D1L24 # D1L30 # D1_i2c_state.write_data & D1L37;


--D1L314 is i2c:inst4|sda_buf~140
--operation mode is normal

D1L314 = D1_phase0 & A1L6 # !D1_phase0 & (D1_sda_buf);


--D1L39 is i2c:inst4|Select~12558
--operation mode is normal

D1L39 = D1_inner_state.ack & (D1_phase3 # D1L314) # !D1L29;


--D1L40 is i2c:inst4|Select~12559
--operation mode is normal

D1L40 = D1_inner_state.stop & (D1_sda_buf # D1_phase1) # !D1_inner_state.stop & D1_sda_buf & (!D1_inner_state.start);


--D1L41 is i2c:inst4|Select~12560
--operation mode is normal

D1L41 = D1L139 # D1L314 & (D1_inner_state.eighth # !D1L36);


--D1L42 is i2c:inst4|Select~12561
--operation mode is normal

D1L42 = D1_i2c_state.read_data & (D1L41 # D1_i2c_state.sendaddr & D1L39) # !D1_i2c_state.read_data & D1_i2c_state.sendaddr & D1L39;


--D1L43 is i2c:inst4|Select~12562
--operation mode is normal

D1L43 = D1_i2c_state.write_data & D1_sda_buf # !D1_main_state.10;


--D1L44 is i2c:inst4|Select~12563
--operation mode is normal

D1L44 = D1_sda_buf & (D1_inner_state.seventh # D1_inner_state.second) # !D1_sda_buf & D1_phase3 & (D1_inner_state.seventh # D1_inner_state.second);


--D1L45 is i2c:inst4|Select~12564
--operation mode is normal

D1L45 = D1L17 # D1L44 # D1L21 & D1_sda_buf;


--D1L46 is i2c:inst4|Select~12565
--operation mode is normal

D1L46 = D1L18 # D1L313 & (!D1L20 # !D1L19);


--D1L47 is i2c:inst4|Select~12566
--operation mode is normal

D1L47 = D1L43 # D1_i2c_state.read_ini & (D1L45 # D1L46);


--D1L48 is i2c:inst4|Select~12567
--operation mode is normal

D1L48 = D1L38 & (D1L42 # D1L24 # D1L47);


--D1L12 is i2c:inst4|Equal~734
--operation mode is normal

D1L12 = D1_clk_div[3] & (!D1_clk_div[7] & !D1_clk_div[0]);


--D1L13 is i2c:inst4|Equal~735
--operation mode is normal

D1L13 = !D1_clk_div[2] & !D1_clk_div[5];


--D1L49 is i2c:inst4|Select~12568
--operation mode is normal

D1L49 = D1_inner_state.ack & D1_i2c_state.sendaddr & D1_phase3;


--D1L50 is i2c:inst4|Select~12569
--operation mode is normal

D1L50 = D1_inner_state.ack & D1_phase3;


--D1L51 is i2c:inst4|Select~12570
--operation mode is normal

D1L51 = D1_main_state.10 & (D1_inner_state.stop # D1_i2c_state.read_data & D1L50);


--D1L52 is i2c:inst4|Select~12571
--operation mode is normal

D1L52 = D1_inner_state.ack & D1_i2c_state.write_data;