cycloneiii_3c25_start_niosii_standard_sopc.ptf

来自「nios里面用自定义指令集来实现三角函数」· PTF 代码 · 共 2,232 行 · 第 1/5 页

SYSTEM cycloneIII_3c25_start_niosII_standard_sopc
{
   System_Wizard_Version = "7.20";
   System_Wizard_Build = "175";
   Builder_Application = "sopc_builder_ca";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      hdl_language = "verilog";
      device_family = "CYCLONEIII";
      device_family_id = "CYCLONEIII";
      generate_sdk = "0";
      do_build_sim = "0";
      hardcopy_compatible = "0";
      CLOCKS 
      {
         CLOCK osc_clk
         {
            frequency = "50000000";
            source = "External";
            Is_Clock_Source = "0";
            display_name = "osc_clk";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "osc_clk.clk";
         }
         CLOCK altmemddr_phy_clk
         {
            frequency = "110000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "phy_clk from altmemddr";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "altmemddr.sysclk";
         }
         CLOCK altmemddr_phy_clk_out
         {
            frequency = "110000000";
            source = "altmemddr_phy_clk";
            Is_Clock_Source = "0";
            display_name = "altmemddr_phy_clk_out";
         }
         CLOCK sys_pll_c0
         {
            frequency = "100000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c0 from sys_pll";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "sys_pll.c0";
         }
         CLOCK system_clk
         {
            frequency = "100000000";
            source = "sys_pll_c0";
            Is_Clock_Source = "0";
            display_name = "system_clk";
         }
         CLOCK sys_pll_c1
         {
            frequency = "100000000";
            source = "";
            Is_Clock_Source = "1";
            display_name = "c1 from sys_pll";
            pipeline = "0";
            clock_module_connection_point_for_c2h = "sys_pll.c1";
         }
         CLOCK ssram_clk
         {
            frequency = "100000000";
            source = "sys_pll_c1";
            Is_Clock_Source = "0";
            display_name = "ssram_clk";
         }
      }
      clock_freq = "50000000";
      clock_freq = "50000000";
      board_class = "";
      view_master_columns = "1";
      view_master_priorities = "0";
      generate_hdl = "";
      bustype_column_width = "0";
      clock_column_width = "80";
      name_column_width = "75";
      desc_column_width = "75";
      base_column_width = "75";
      end_column_width = "75";
      BOARD_INFO 
      {
         altera_avalon_cfi_flash 
         {
            reference_designators = "";
         }
      }
      do_log_history = "0";
   }
   MODULE cpu
   {
      MASTER instruction_master
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT reset_n
            {
               type = "reset_n";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT i_address
            {
               type = "address";
               width = "28";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT i_read
            {
               type = "read";
               width = "1";
               direction = "output";
               Is_Enabled = "1";
            }
            PORT i_readdata
            {
               type = "readdata";
               width = "32";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_readdatavalid
            {
               type = "readdatavalid";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
            PORT i_waitrequest
            {
               type = "waitrequest";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Do_Stream_Reads = "0";
            Do_Stream_Writes = "0";
            Max_Address_Width = "32";
            Data_Width = "32";
            Address_Width = "28";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "";
            Linewrap_Bursts = "";
            Burst_On_Burst_Boundaries_Only = "";
            Always_Burst_Max_Burst = "";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Is_Instruction_Master = "1";
            Is_Readable = "1";
            Is_Writeable = "0";
            Address_Group = "0";
            Has_IRQ = "0";
            Irq_Scheme = "individual_requests";
            Interrupt_Range = "0-0";
         }
         MEMORY_MAP 
         {
            Entry altmemddr_bridge/s1
            {
               address = "0x02000000";
               span = "0x02000000";
            }
            Entry altmemddr/s1
            {
               address = "0x02000000";
               span = "0x02000000";
            }
            Entry cpu/jtag_debug_module
            {
               address = "0x09008800";
               span = "0x00000800";
            }
            Entry pipeline_bridge_before_atb/s1
            {
               address = "0x06000000";
               span = "0x02000000";
            }
            Entry ext_ssram/s1
            {
               address = "0x07000000";
               span = "0x00100000";
            }
            Entry ext_flash/s1
            {
               address = "0x06000000";
               span = "0x01000000";
            }
         }
      }
      MASTER custom_instruction_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Is_Custom_Instruction = "1";
            Is_Enabled = "1";
            Max_Address_Width = "8";
            Base_Address = "N/A";
            Is_Visible = "0";
         }
         PORT_WIRING 
         {
            PORT dataa
            {
               type = "dataa";
               width = "32";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT datab
            {
               type = "datab";
               width = "32";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT result
            {
               type = "result";
               width = "32";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT clk_en
            {
               type = "clk_en";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT reset
            {
               type = "reset";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT start
            {
               type = "start";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT done
            {
               type = "done";
               width = "1";
               direction = "input";
               Is_Enabled = "0";
            }
            PORT n
            {
               type = "n";
               width = "8";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT a
            {
               type = "a";
               width = "5";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT b
            {
               type = "b";
               width = "5";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT c
            {
               type = "c";
               width = "5";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT readra
            {
               type = "readra";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT readrb
            {
               type = "readrb";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT writerc
            {
               type = "writerc";
               width = "1";
               direction = "output";
               Is_Enabled = "0";
            }
            PORT A_ci_multi_a
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_a";
               width = "5";
            }
            PORT A_ci_multi_b
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_b";
               width = "5";
            }
            PORT A_ci_multi_c
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_c";
               width = "5";
            }
            PORT A_ci_multi_clk_en
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_clk_en";
               width = "1";
            }
            PORT A_ci_multi_dataa
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_dataa";
               width = "32";
            }
            PORT A_ci_multi_datab
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_datab";
               width = "32";
            }
            PORT A_ci_multi_done
            {
               Is_Enabled = "1";
               direction = "input";
               type = "multi_done";
               width = "1";
            }
            PORT A_ci_multi_estatus
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_estatus";
               width = "1";
            }
            PORT A_ci_multi_ipending
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_ipending";
               width = "32";
            }
            PORT A_ci_multi_n
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_n";
               width = "8";
            }
            PORT A_ci_multi_readra
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_readra";
               width = "1";
            }
            PORT A_ci_multi_readrb
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_readrb";
               width = "1";
            }
            PORT A_ci_multi_result
            {
               Is_Enabled = "1";
               direction = "input";
               type = "multi_result";
               width = "32";
            }
            PORT A_ci_multi_start
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_start";
               width = "1";
            }
            PORT A_ci_multi_status
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_status";
               width = "1";
            }
            PORT A_ci_multi_writerc
            {
               Is_Enabled = "1";
               direction = "output";
               type = "multi_writerc";
               width = "1";
            }
            PORT clk
            {
               Is_Enabled = "1";
               direction = "input";
               type = "clk";
               width = "1";
            }
            PORT reset_n
            {
               Is_Enabled = "1";