cycloneiii_3c25_start_niosii_standard_sopc.ptf

来自「nios里面用自定义指令集来实现三角函数」· PTF 代码 · 共 2,232 行 · 第 1/5 页

PTF
2,232 行
字号
               radix = "hexadecimal";
            }
            SIGNAL acp
            {
               format = "Logic";
               name = "F_kill";
               radix = "hexadecimal";
            }
            SIGNAL acq
            {
               format = "Logic";
               name = "D_kill";
               radix = "hexadecimal";
            }
            SIGNAL acr
            {
               format = "Logic";
               name = "D_refetch";
               radix = "hexadecimal";
            }
            SIGNAL acs
            {
               format = "Logic";
               name = "D_issue";
               radix = "hexadecimal";
            }
            SIGNAL act
            {
               format = "Logic";
               name = "D_valid";
               radix = "hexadecimal";
            }
            SIGNAL acu
            {
               format = "Logic";
               name = "E_valid";
               radix = "hexadecimal";
            }
            SIGNAL acv
            {
               format = "Logic";
               name = "M_valid";
               radix = "hexadecimal";
            }
            SIGNAL acw
            {
               format = "Logic";
               name = "A_valid";
               radix = "hexadecimal";
            }
            SIGNAL acx
            {
               format = "Logic";
               name = "W_valid";
               radix = "hexadecimal";
            }
            SIGNAL acy
            {
               format = "Logic";
               name = "W_wr_dst_reg";
               radix = "hexadecimal";
            }
            SIGNAL acz
            {
               format = "Logic";
               name = "W_dst_regnum";
               radix = "hexadecimal";
            }
            SIGNAL ada
            {
               format = "Logic";
               name = "W_wr_data";
               radix = "hexadecimal";
            }
            SIGNAL adb
            {
               format = "Logic";
               name = "D_en";
               radix = "hexadecimal";
            }
            SIGNAL adc
            {
               format = "Logic";
               name = "E_en";
               radix = "hexadecimal";
            }
            SIGNAL add
            {
               format = "Logic";
               name = "M_en";
               radix = "hexadecimal";
            }
            SIGNAL ade
            {
               format = "Logic";
               name = "A_en";
               radix = "hexadecimal";
            }
            SIGNAL adf
            {
               format = "Logic";
               name = "F_iw";
               radix = "hexadecimal";
            }
            SIGNAL adg
            {
               format = "Logic";
               name = "D_iw";
               radix = "hexadecimal";
            }
            SIGNAL adh
            {
               format = "Logic";
               name = "E_iw";
               radix = "hexadecimal";
            }
            SIGNAL adi
            {
               format = "Logic";
               name = "M_pipe_flush";
               radix = "hexadecimal";
            }
            SIGNAL adj
            {
               format = "Logic";
               name = "M_pipe_flush_baddr";
               radix = "hexadecimal";
            }
            SIGNAL adk
            {
               format = "Logic";
               name = "A_ienable_reg";
               radix = "hexadecimal";
            }
            SIGNAL adl
            {
               format = "Logic";
               name = "A_status_reg_pie";
               radix = "hexadecimal";
            }
            SIGNAL adm
            {
               format = "Logic";
               name = "intr_req";
               radix = "hexadecimal";
            }
            SIGNAL adn
            {
               format = "Logic";
               name = "E_valid_prior_to_hbreak";
               radix = "hexadecimal";
            }
            SIGNAL ado
            {
               format = "Divider";
               name = "multicycle_custom_instruction";
               radix = "";
            }
            SIGNAL adp
            {
               format = "Logic";
               name = "A_ctrl_custom_multi";
               radix = "hexadecimal";
            }
            SIGNAL adq
            {
               format = "Logic";
               name = "A_ci_multi_dataa";
               radix = "hexadecimal";
            }
            SIGNAL adr
            {
               format = "Logic";
               name = "A_ci_multi_datab";
               radix = "hexadecimal";
            }
            SIGNAL ads
            {
               format = "Logic";
               name = "A_ci_multi_ipending";
               radix = "hexadecimal";
            }
            SIGNAL adt
            {
               format = "Logic";
               name = "A_ci_multi_status";
               radix = "hexadecimal";
            }
            SIGNAL adu
            {
               format = "Logic";
               name = "A_ci_multi_estatus";
               radix = "hexadecimal";
            }
            SIGNAL adv
            {
               format = "Logic";
               name = "A_ci_multi_n";
               radix = "hexadecimal";
            }
            SIGNAL adw
            {
               format = "Logic";
               name = "A_ci_multi_readra";
               radix = "hexadecimal";
            }
            SIGNAL adx
            {
               format = "Logic";
               name = "A_ci_multi_readrb";
               radix = "hexadecimal";
            }
            SIGNAL ady
            {
               format = "Logic";
               name = "A_ci_multi_writerc";
               radix = "hexadecimal";
            }
            SIGNAL adz
            {
               format = "Logic";
               name = "A_ci_multi_result";
               radix = "hexadecimal";
            }
            SIGNAL aea
            {
               format = "Logic";
               name = "A_ci_multi_clk_en";
               radix = "hexadecimal";
            }
            SIGNAL aeb
            {
               format = "Logic";
               name = "A_ci_multi_start";
               radix = "hexadecimal";
            }
            SIGNAL aec
            {
               format = "Logic";
               name = "A_ci_multi_done";
               radix = "hexadecimal";
            }
            SIGNAL aed
            {
               format = "Logic";
               name = "A_ci_multi_stall";
               radix = "hexadecimal";
            }
         }
      }
   }
   MODULE flash_ssram_tristate_bridge
   {
      SLAVE avalon_slave
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "1cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1";
            Read_Latency = "0";
            Is_Memory_Device = "0";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_Internal_Connections = "1";
            Write_Latency = "0";
            Is_Flash = "0";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "1";
            Register_Outgoing_Signals = "1";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            MASTERED_BY pipeline_bridge_before_atb/m1
            {
               priority = "1";
               Offset_Address = "0x00000000";
            }
            Bridges_To = "tristate_master";
            Base_Address = "N/A";
            Has_IRQ = "0";
            IRQ = "N/A";
            Address_Group = "0";
         }
      }
      MASTER tristate_master
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Asynchronous = "0";
            DBS_Big_Endian = "0";
            Adapts_To = "";
            Maximum_Burst_Size = "1";
            Register_Incoming_Signals = "0";
            Register_Outgoing_Signals = "0";
            Interleave_Bursts = "0";
            Linewrap_Bursts = "0";
            Burst_On_Burst_Boundaries_Only = "0";
            Always_Burst_Max_Burst = "0";
            Is_Big_Endian = "0";
            Is_Enabled = "1";
            Bridges_To = "avalon_slave";
         }
         PORT_WIRING 
         {
         }
         MEMORY_MAP 
         {
            Entry ext_ssram/s1
            {
               address = "0x01000000";
               span = "0x00100000";
            }
            Entry ext_flash/s1
            {
               address = "0x00000000";
               span = "0x01000000";
            }
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      class = "altera_avalon_tri_state_bridge";
      class_version = "7.071";
      SYSTEM_BUILDER_INFO 
      {
         Is_Enabled = "1";
         Clock_Source = "system_clk";
         Has_Clock = "1";
         Instantiate_In_System_Module = "1";
         Is_Bridge = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         View 
         {
            MESSAGES 
            {
            }
         }
      }
   }
   MODULE ext_ssram
   {
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT clk
            {
               type = "clk";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "1";
               visible = "0";
            }
            PORT address
            {
               type = "address";
               width = "18";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "1";
            }
            PORT adsc_n
            {
               type = "begintransfer_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT bw_n
            {
               type = "byteenable_n";
               width = "4";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT bwe_n
            {
               type = "write_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT chipenable1_n
            {
               type = "chipselect_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
            PORT data
            {
               type = "data";
               width = "32";
               direction = "inout";
               Is_Enabled = "1";
               is_shared = "1";
            }
            PORT outputenable_n
            {
               type = "outputenable_n";
               width = "1";
               direction = "input";
               Is_Enabled = "1";
               is_shared = "0";
            }
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Write_Wait_States = "0cycles";
            Read_Wait_States = "0cycles";
            Hold_Time = "0cycles";
            Setup_Time = "0cycles";
            Is_Printable_Device = "0";
            Address_Alignment = "dynamic";
            Well_Behaved_Waitrequest = "0";
            Is_Nonvolatile_Storage = "0";
            Address_Span = "1048576";
            Read_Latency = "2";
            Is_Memory_Device = "1";
            Maximum_Pending_Read_Transactions = "0";
            Minimum_Uninterrupted_Run_Length = "1";
            Accepts_In

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