hal_uart.s51

来自「TI的基于ZIGBEE2006的协议栈」· S51 代码 · 共 1,640 行 · 第 1/5 页

//  202   uint16 txMax;
//  203   uint16 txCnt;
//  204 #else
//  205   uint8 txHead;
//  206   uint8 txTail;
//  207   uint8 txMax;
//  208   uint8 txCnt;
//  209 #endif
//  210   uint8 txTick;
//  211 
//  212   uint8 flag;
//  213 
//  214   halUARTCBack_t rxCB;
//  215 } uartCfg_t;
//  216 
//  217 /*********************************************************************
//  218  * CONSTANTS
//  219  */
//  220 
//  221 // Used by DMA macros to shift 1 to create a mask for DMA registers.
//  222 #define HAL_DMA_CH_TX    3
//  223 #define HAL_DMA_CH_RX    4
//  224 
//  225 #define HAL_DMA_U0DBUF  0xDFC1
//  226 #define HAL_DMA_U1DBUF  0xDFF9
//  227 
//  228 // UxCSR - USART Control and Status Register.
//  229 #define CSR_MODE      0x80
//  230 #define CSR_RE        0x40
//  231 #define CSR_SLAVE     0x20
//  232 #define CSR_FE        0x10
//  233 #define CSR_ERR       0x08
//  234 #define CSR_RX_BYTE   0x04
//  235 #define CSR_TX_BYTE   0x02
//  236 #define CSR_ACTIVE    0x01
//  237 
//  238 // UxUCR - USART UART Control Register.
//  239 #define UCR_FLUSH     0x80
//  240 #define UCR_FLOW      0x40
//  241 #define UCR_D9        0x20
//  242 #define UCR_BIT9      0x10
//  243 #define UCR_PARITY    0x08
//  244 #define UCR_SPB       0x04
//  245 #define UCR_STOP      0x02
//  246 #define UCR_START     0x01
//  247 
//  248 #define UTX0IE        0x04
//  249 #define UTX1IE        0x08
//  250 
//  251 #define UART_CFG_U1F  0x80  // USART1 flag bit.
//  252 #define UART_CFG_DMA  0x40  // Port is using DMA.
//  253 #define UART_CFG_FLW  0x20  // Port is using flow control.
//  254 #define UART_CFG_SP4  0x10
//  255 #define UART_CFG_SP3  0x08
//  256 #define UART_CFG_SP2  0x04
//  257 #define UART_CFG_RXF  0x02  // Rx flow is disabled.
//  258 #define UART_CFG_TXF  0x01  // Tx is in process.
//  259 
//  260 /*********************************************************************
//  261  * GLOBAL VARIABLES
//  262  */
//  263 
//  264 /*********************************************************************
//  265  * GLOBAL FUNCTIONS
//  266  */
//  267 
//  268 /*********************************************************************
//  269  * LOCAL VARIABLES
//  270  */
//  271 
//  272 #if HAL_UART_0_ENABLE

        RSEG XDATA_Z:XDATA:NOROOT(0)
        REQUIRE __INIT_XDATA_Z
//  273 static uartCfg_t *cfg0;
??cfg0:
        DS 2
//  274 #endif
//  275 #if HAL_UART_1_ENABLE
//  276 static uartCfg_t *cfg1;
//  277 #endif
//  278 
//  279 /*********************************************************************
//  280  * LOCAL FUNCTIONS
//  281  */
//  282 
//  283 #if HAL_UART_DMA
//  284 static void pollDMA( uartCfg_t *cfg );
//  285 #endif
//  286 #if HAL_UART_ISR
//  287 static void pollISR( uartCfg_t *cfg );
//  288 #endif
//  289 
//  290 #if HAL_UART_DMA
//  291 /******************************************************************************
//  292  * @fn      pollDMA
//  293  *
//  294  * @brief   Poll a USART module implemented by DMA.
//  295  *
//  296  * @param   cfg - USART configuration structure.
//  297  *
//  298  * @return  none
//  299  *****************************************************************************/

        RSEG BANKED_CODE:CODE:NOROOT(0)
//  300 static void pollDMA( uartCfg_t *cfg )
??pollDMA:
        CFI Block cfiBlock0 Using cfiCommon0
        CFI Function ??pollDMA
//  301 {
        FUNCALL ??pollDMA, osal_memset
        LOCFRAME XSTACK, 11, STACK
        ARGFRAME XSTACK, 11, STACK
        MOV	A,#-0xa
        LCALL	?BANKED_ENTER_XDATA
        CFI DPH0 load(1, XDATA, add(CFA_XSP16, literal(-1)))
        CFI DPL0 load(1, XDATA, add(CFA_XSP16, literal(-2)))
        CFI ?BRET_EXT load(1, XDATA, add(CFA_XSP16, literal(-3)))
        CFI ?RET_HIGH load(1, XDATA, add(CFA_XSP16, literal(-4)))
        CFI ?RET_LOW load(1, XDATA, add(CFA_XSP16, literal(-5)))
        CFI R7 load(1, XDATA, add(CFA_XSP16, literal(-6)))
        CFI V1 load(1, XDATA, add(CFA_XSP16, literal(-7)))
        CFI V0 load(1, XDATA, add(CFA_XSP16, literal(-8)))
        CFI VB load(1, XDATA, add(CFA_XSP16, literal(-9)))
        CFI R6 load(1, XDATA, add(CFA_XSP16, literal(-10)))
        CFI CFA_SP SP+0
        CFI CFA_XSP16 add(XSP16, 10)
        ; Saved register size: 10
        ; Auto size: 1
        MOV	A,#-0x1
        LCALL	?ALLOC_XSTACK8
        CFI CFA_XSP16 add(XSP16, 11)
        MOV	A,R2
        MOV	R6,A
        MOV	A,R3
        MOV	R7,A
//  302   const uint8 cnt = cfg->rxHead;
        MOV	A,R6
        ADD	A,#0x2
        INC	R2
        INC	R2
        LCALL	?Subroutine6 & 0xFFFF
//  303   uint8 *pad = cfg->rxBuf+(cfg->rxHead*2);
??CrossCallReturnLabel_32:
        CLR	C
        RLC	A
        MOV	R0,A
        CLR	A
        RLC	A
        MOV	R1,A
        MOV	DPL,R6
        MOV	DPH,R7
        MOVX	A,@DPTR
        ADD	A,R0
        MOV	R0,A
        INC	DPTR
        MOVX	A,@DPTR
        ADDC	A,R1
        SJMP	??pollDMA_1
//  304 
//  305   // Pack the received bytes to the front of the queue.
//  306   while ( (*pad == DMA_PAD) && (cfg->rxHead < cfg->rxMax) )
//  307   {
//  308     cfg->rxBuf[cfg->rxHead++] = *(pad+1);
??pollDMA_2:
        MOV	A,R6
        ADD	A,#0x2
        MOV	R2,A
        MOV	DPL,R0
        MOV	DPH,R1
        INC	DPTR
        MOVX	A,@DPTR
        PUSH	A
        CFI CFA_SP SP+-1
        MOV	DPL,R2
        MOV	DPH,R3
        MOVX	A,@DPTR
        MOV	?V0 + 0,A
        MOV	DPL,R6
        MOV	DPH,R7
        MOVX	A,@DPTR
        ADD	A,?V0 + 0
        MOV	R5,A
        INC	DPTR
        MOVX	A,@DPTR
        ADDC	A,#0x0
        MOV	DPL,R5
        MOV	DPH,A
        POP	A
        CFI CFA_SP SP+0
        MOVX	@DPTR,A
        MOV	DPL,R2
        MOV	DPH,R3
        MOVX	A,@DPTR
        INC	A
        MOVX	@DPTR,A
//  309     pad += 2;
        MOV	A,R0
        ADD	A,#0x2
        INC	R0
        INC	R0
        MOV	A,R1
        ADDC	A,#0x0
??pollDMA_1:
        MOV	R1,A
//  310   }
        MOV	DPL,R0
        MOV	DPH,R1
        MOVX	A,@DPTR
        XRL	A,0xc2
        JNZ	??pollDMA_3
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        MOVX	A,@DPTR
        PUSH	A
        CFI CFA_SP SP+-1
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        MOVX	A,@DPTR
        MOV	R2,A
        POP	A
        CFI CFA_SP SP+0
        CLR	C
        SUBB	A,R2
        JC	??pollDMA_2
//  311 
//  312   if ( !(cfg->flag & UART_CFG_RXF) )
??pollDMA_3:
        LCALL	?Subroutine5 & 0xFFFF
??CrossCallReturnLabel_13:
        MOV	C,0xE0 /* A   */.1
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        JC	??pollDMA_4
//  313   {
//  314     /* It is necessary to stop Rx flow and wait for H/W-enqueued bytes still
//  315      * incoming to stop before resetting the DMA Rx engine. If DMA Rx is
//  316      * aborted during incoming data, a byte may be lost inside the engine
//  317      * during the 2-step transfer process of read/write.
//  318      */
//  319     if ( cfg->rxHead >= (cfg->rxMax - SAFE_RX_MIN) )
        MOVX	A,@DPTR
        MOV	R2,A
        MOV	DPL,R6
        MOV	DPH,R7
        LCALL	?Subroutine1 & 0xFFFF
??CrossCallReturnLabel_0:
        JC	??pollDMA_5
//  320     {
//  321       RX_STOP_FLOW( cfg );
        LCALL	?Subroutine4 & 0xFFFF
??CrossCallReturnLabel_10:
        JC	??pollDMA_6
        SETB	0x80.5
        SJMP	??pollDMA_7
??pollDMA_6:
        SETB	0x90.5
??pollDMA_7:
        MOV	C,0xE0 /* A   */.6
        JNC	??pollDMA_8
        MOV	A,#-0x74
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        MOVX	@DPTR,A
??pollDMA_8:
        LCALL	?Subroutine5 & 0xFFFF
??CrossCallReturnLabel_14:
        SETB	0xE0 /* A   */.1
        SJMP	??pollDMA_9
//  322     }
//  323     // If anything received, reset the Rx idle timer.
//  324     else if ( cfg->rxHead != cnt )
??pollDMA_5:
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        MOVX	A,@DPTR
        XRL	A,R4
        JZ	??pollDMA_10
//  325     {
//  326       cfg->rxTick = HAL_UART_RX_IDLE;
        MOV	A,#-0x3a
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        SJMP	??pollDMA_9
//  327     }
//  328   }
//  329   else if ( !cfg->rxTick && (cfg->rxHead == cfg->rxTail) )
??pollDMA_4:
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        MOVX	A,@DPTR
        JNZ	??pollDMA_10
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        LCALL	?Subroutine16 & 0xFFFF
??CrossCallReturnLabel_54:
        MOVX	A,@DPTR
        XRL	A,R2
        JNZ	??pollDMA_10
//  330   {
//  331     HAL_DMA_ABORT_CH( HAL_DMA_CH_RX );
        MOV	0xd6,#-0x70