hal_uart.s51
来自「TI的基于ZIGBEE2006的协议栈」· S51 代码 · 共 1,640 行 · 第 1/5 页
S51
1,640 行
CFI `B.BR0` SameValue
CFI `B.BR1` SameValue
CFI `B.BR2` SameValue
CFI `B.BR3` SameValue
CFI `B.BR4` SameValue
CFI `B.BR5` SameValue
CFI `B.BR6` SameValue
CFI `B.BR7` SameValue
CFI `VB.BR8` SameValue
CFI `VB.BR9` SameValue
CFI `VB.BR10` SameValue
CFI `VB.BR11` SameValue
CFI `VB.BR12` SameValue
CFI `VB.BR13` SameValue
CFI `VB.BR14` SameValue
CFI `VB.BR15` SameValue
CFI VB SameValue
CFI B SameValue
CFI A SameValue
CFI PSW SameValue
CFI DPL0 SameValue
CFI DPH0 SameValue
CFI R0 SameValue
CFI R1 SameValue
CFI R2 SameValue
CFI R3 SameValue
CFI R4 SameValue
CFI R5 SameValue
CFI R6 SameValue
CFI R7 SameValue
CFI V0 SameValue
CFI V1 SameValue
CFI V2 SameValue
CFI V3 SameValue
CFI V4 SameValue
CFI V5 SameValue
CFI V6 SameValue
CFI V7 SameValue
CFI PSPH Undefined
CFI PSPL Undefined
CFI XSPH Undefined
CFI XSPL Undefined
CFI ?RET Concat
CFI ?BRET_EXT SameValue
CFI ?RET_HIGH Frame(CFA_SP, 2)
CFI ?RET_LOW Frame(CFA_SP, 1)
CFI EndCommon cfiCommon1
EXTERN osal_memset
FUNCTION osal_memset,0202H
ARGFRAME XSTACK, 15, STACK
EXTERN osal_mem_alloc
FUNCTION osal_mem_alloc,0202H
ARGFRAME XSTACK, 15, STACK
EXTERN dmaCh1234
// C:\Texas Instruments\ZStack-1.4.2\Components\hal\target\CC2430EB\hal_uart.c
// 1 /******************************************************************************
// 2 Filename: _hal_uart.c
// 3 Revised: $Date: 2007-03-26 11:53:55 -0700 (Mon, 26 Mar 2007) $
// 4 Revision: $Revision: 13853 $
// 5
// 6 Description: This file contains the interface to the H/W UART driver.
// 7
// 8 Copyright (c) 2007 by Texas Instruments, Inc.
// 9 All Rights Reserved. Permission to use, reproduce, copy, prepare
// 10 derivative works, modify, distribute, perform, display or sell this
// 11 software and/or its documentation for any purpose is prohibited
// 12 without the express written consent of Texas Instruments, Inc.
// 13 ******************************************************************************/
// 14
// 15 /*********************************************************************
// 16 * INCLUDES
// 17 */
// 18
// 19 #include "hal_types.h"
// 20 #include "hal_assert.h"
// 21 #include "hal_board.h"
ASEGN SFR_AN:DATA:NOROOT,086H
// unsigned char volatile __sfr U0CSR
U0CSR:
DS 1
ASEGN SFR_AN:DATA:NOROOT,095H
// unsigned char volatile __sfr ST0
ST0:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0c1H
// unsigned char volatile __sfr U0DBUF
U0DBUF:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0c2H
// unsigned char volatile __sfr U0BAUD
U0BAUD:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0c4H
// unsigned char volatile __sfr U0UCR
U0UCR:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0c5H
// unsigned char volatile __sfr U0GCR
U0GCR:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0d1H
// unsigned char volatile __sfr DMAIRQ
DMAIRQ:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0d6H
// unsigned char volatile __sfr DMAARM
DMAARM:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0d7H
// unsigned char volatile __sfr DMAREQ
DMAREQ:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0f1H
// unsigned char volatile __sfr PERCFG
PERCFG:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0f2H
// unsigned char volatile __sfr ADCCFG
ADCCFG:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0f3H
// unsigned char volatile __sfr P0SEL
P0SEL:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0fdH
// unsigned char volatile __sfr P0DIR
P0DIR:
DS 1
ASEGN SFR_AN:DATA:NOROOT,0ffH
// unsigned char volatile __sfr P2DIR
P2DIR:
DS 1
// 22 #include "hal_defs.h"
// 23 #if defined( HAL_UART_DMA ) && HAL_UART_DMA
// 24 #include "hal_dma.h"
// 25 #endif
// 26 #include "hal_mcu.h"
// 27 #include "hal_uart.h"
// 28 #include "osal.h"
// 29
// 30 /*********************************************************************
// 31 * MACROS
// 32 */
// 33
// 34 #if !defined ( HAL_UART_DEBUG )
// 35 #define HAL_UART_DEBUG FALSE
// 36 #endif
// 37
// 38 #if !defined ( HAL_UART_CLOSE )
// 39 #define HAL_UART_CLOSE FALSE
// 40 #endif
// 41
// 42 #if !defined ( HAL_UART_BIG_TX_BUF )
// 43 #define HAL_UART_BIG_TX_BUF FALSE
// 44 #endif
// 45
// 46 /*
// 47 * The MAC_ASSERT macro is for use during debugging.
// 48 * The given expression must evaluate as "true" or else fatal error occurs.
// 49 * At that point, the call stack feature of the debugger can pinpoint where
// 50 * the problem occurred.
// 51 *
// 52 * To disable this feature and save code size, the project should define
// 53 * HAL_UART_DEBUG to FALSE.
// 54 */
// 55 #if ( HAL_UART_DEBUG )
// 56 #define HAL_UART_ASSERT( expr) HAL_ASSERT( expr )
// 57 #else
// 58 #define HAL_UART_ASSERT( expr )
// 59 #endif
// 60
// 61 #define P2DIR_PRIPO 0xC0
// 62 #if HAL_UART_0_ENABLE
// 63 #define HAL_UART_PRIPO 0x00
// 64 #else
// 65 #define HAL_UART_PRIPO 0x40
// 66 #endif
// 67
// 68 #define HAL_UART_0_PERCFG_BIT 0x01 // USART0 on P0, so clear this bit.
// 69 #define HAL_UART_0_P0_RX_TX 0x0c // Peripheral I/O Select for Rx/Tx.
// 70 #define HAL_UART_0_P0_RTS 0x10 // Peripheral I/O Select for RTS.
// 71 #define HAL_UART_0_P0_CTS 0x20 // Peripheral I/O Select for CTS.
// 72
// 73 #define HAL_UART_1_PERCFG_BIT 0x02 // USART1 on P1, so set this bit.
// 74 #define HAL_UART_1_P1_RTS 0x10 // Peripheral I/O Select for RTS.
// 75 #define HAL_UART_1_P1_CTS 0x20 // Peripheral I/O Select for CTS.
// 76 #define HAL_UART_1_P1_RX_TX 0xC0 // Peripheral I/O Select for Rx/Tx.
// 77
// 78 #define TX_AVAIL( cfg ) \
// 79 ((cfg->txTail == cfg->txHead) ? (cfg->txMax-1) : \
// 80 ((cfg->txTail > cfg->txHead) ? (cfg->txTail - cfg->txHead - 1) : \
// 81 (cfg->txMax - cfg->txHead + cfg->txTail)))
// 82
// 83 #define RX0_FLOW_ON ( P0 &= ~HAL_UART_0_P0_CTS )
// 84 #define RX0_FLOW_OFF ( P0 |= HAL_UART_0_P0_CTS )
// 85 #define RX1_FLOW_ON ( P1 &= ~HAL_UART_1_P1_CTS)
// 86 #define RX1_FLOW_OFF ( P1 |= HAL_UART_1_P1_CTS )
// 87
// 88 #define RX_STOP_FLOW( cfg ) { \
// 89 if ( !(cfg->flag & UART_CFG_U1F) ) \
// 90 { \
// 91 RX0_FLOW_OFF; \
// 92 } \
// 93 else \
// 94 { \
// 95 RX1_FLOW_OFF; \
// 96 } \
// 97 if ( cfg->flag & UART_CFG_DMA ) \
// 98 { \
// 99 cfg->rxTick = DMA_RX_DLY; \
// 100 } \
// 101 cfg->flag |= UART_CFG_RXF; \
// 102 }
// 103
// 104 #define RX_STRT_FLOW( cfg ) { \
// 105 if ( !(cfg->flag & UART_CFG_U1F) ) \
// 106 { \
// 107 RX0_FLOW_ON; \
// 108 } \
// 109 else \
// 110 { \
// 111 RX1_FLOW_ON; \
// 112 } \
// 113 cfg->flag &= ~UART_CFG_RXF; \
// 114 }
// 115
// 116 #define UART_RX_AVAIL( cfg ) \
// 117 ( (cfg->rxHead >= cfg->rxTail) ? (cfg->rxHead - cfg->rxTail) : \
// 118 (cfg->rxMax - cfg->rxTail + cfg->rxHead +1 ) )
// 119
// 120 /* Need to leave enough of the Rx buffer free to handle the incoming bytes
// 121 * after asserting flow control, but before the transmitter has obeyed it.
// 122 * At the max expected baud rate of 115.2k, 16 bytes will only take ~1.3 msecs,
// 123 * but at the min expected baud rate of 38.4k, they could take ~4.2 msecs.
// 124 * SAFE_RX_MIN and DMA_RX_DLY must both be consistent according to
// 125 * the min & max expected baud rate.
// 126 */
// 127 #if !defined( SAFE_RX_MIN )
// 128 #define SAFE_RX_MIN 48 // bytes - max expected per poll @ 115.2k
// 129 // 16 bytes @ 38.4 kBaud -> 4.16 msecs -> 138 32-kHz ticks.
// 130 #define DMA_RX_DLY 140
// 131 // 2 bytes @ 38.4 kBaud -> 0.52 msecs -> 17 32-kHz ticks.
// 132 #define DMA_TX_DLY 20
// 133 #endif
// 134
// 135 // The timeout tick is at 32-kHz, so multiply msecs by 33.
// 136 #define RX_MSECS_TO_TICKS 33
// 137
// 138 // The timeout only supports 1 byte.
// 139 #if !defined( HAL_UART_RX_IDLE )
// 140 #define HAL_UART_RX_IDLE (6 * RX_MSECS_TO_TICKS)
// 141 #endif
// 142
// 143 // Only supporting 1 of the 2 USART modules to be driven by DMA at a time.
// 144 #if HAL_UART_DMA == 1
// 145 #define DMATRIG_RX HAL_DMA_TRIG_URX0
// 146 #define DMATRIG_TX HAL_DMA_TRIG_UTX0
// 147 #define DMA_UDBUF HAL_DMA_U0DBUF
// 148 #define DMA_PAD U0BAUD
// 149 #elif HAL_UART_DMA == 2
// 150 #define DMATRIG_RX HAL_DMA_TRIG_URX1
// 151 #define DMATRIG_TX HAL_DMA_TRIG_UTX1
// 152 #define DMA_UDBUF HAL_DMA_U1DBUF
// 153 #define DMA_PAD U1BAUD
// 154 #endif
// 155
// 156 #define DMA_RX( cfg ) { \
// 157 volatile uint8 ft2430 = U0DBUF; \
// 158 \
// 159 halDMADesc_t *ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_RX ); \
// 160 \
// 161 HAL_DMA_SET_DEST( ch, cfg->rxBuf ); \
// 162 \
// 163 HAL_DMA_SET_LEN( ch, cfg->rxMax ); \
// 164 \
// 165 HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_RX ); \
// 166 \
// 167 HAL_DMA_ARM_CH( HAL_DMA_CH_RX ); \
// 168 }
// 169
// 170 #define DMA_TX( cfg ) { \
// 171 halDMADesc_t *ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_TX ); \
// 172 \
// 173 HAL_DMA_SET_SOURCE( ch, (cfg->txBuf + cfg->txTail) ); \
// 174 \
// 175 HAL_DMA_SET_LEN( ch, cfg->txCnt ); \
// 176 \
// 177 HAL_DMA_CLEAR_IRQ( HAL_DMA_CH_TX ); \
// 178 \
// 179 HAL_DMA_ARM_CH( HAL_DMA_CH_TX ); \
// 180 \
// 181 HAL_DMA_START_CH( HAL_DMA_CH_TX ); \
// 182 }
// 183
// 184 /*********************************************************************
// 185 * TYPEDEFS
// 186 */
// 187
// 188 typedef struct
// 189 {
// 190 uint8 *rxBuf;
// 191 uint8 rxHead;
// 192 uint8 rxTail;
// 193 uint8 rxMax;
// 194 uint8 rxCnt;
// 195 uint8 rxTick;
// 196 uint8 rxHigh;
// 197
// 198 uint8 *txBuf;
// 199 #if HAL_UART_BIG_TX_BUF
// 200 uint16 txHead;
// 201 uint16 txTail;
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