autoled.tan.qmsg

共6个尾灯

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "CLK register register AUTOLED:U2\|\\T:LIG\[0\] AUTOLED:U2\|\\T:LIG\[5\] 420.17 MHz Internal " "Info: Clock \"CLK\" Internal fmax is restricted to 420.17 MHz between source register \"AUTOLED:U2\|\\T:LIG\[0\]\" and destination register \"AUTOLED:U2\|\\T:LIG\[5\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.899 ns + Longest register register " "Info: + Longest register to register delay is 1.899 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AUTOLED:U2\|\\T:LIG\[0\] 1 REG LCFF_X63_Y4_N25 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y4_N25; Fanout = 2; REG Node = 'AUTOLED:U2\|\\T:LIG\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.339 ns) + CELL(0.438 ns) 0.777 ns AUTOLED:U2\|Equal1~41 2 COMB LCCOMB_X63_Y4_N6 2 " "Info: 2: + IC(0.339 ns) + CELL(0.438 ns) = 0.777 ns; Loc. = LCCOMB_X63_Y4_N6; Fanout = 2; COMB Node = 'AUTOLED:U2\|Equal1~41'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.777 ns" { AUTOLED:U2|\T:LIG[0] AUTOLED:U2|Equal1~41 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.261 ns) + CELL(0.149 ns) 1.187 ns AUTOLED:U2\|Equal1~42 3 COMB LCCOMB_X63_Y4_N16 4 " "Info: 3: + IC(0.261 ns) + CELL(0.149 ns) = 1.187 ns; Loc. = LCCOMB_X63_Y4_N16; Fanout = 4; COMB Node = 'AUTOLED:U2\|Equal1~42'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { AUTOLED:U2|Equal1~41 AUTOLED:U2|Equal1~42 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.150 ns) 1.815 ns AUTOLED:U2\|LIG~631 4 COMB LCCOMB_X63_Y4_N28 1 " "Info: 4: + IC(0.478 ns) + CELL(0.150 ns) = 1.815 ns; Loc. = LCCOMB_X63_Y4_N28; Fanout = 1; COMB Node = 'AUTOLED:U2\|LIG~631'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.628 ns" { AUTOLED:U2|Equal1~42 AUTOLED:U2|LIG~631 } "NODE_NAME" } } { "AUTOLED.vhd" "" { Text "D:/AUTOLED/AUTOLED.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.899 ns AUTOLED:U2\|\\T:LIG\[5\] 5 REG LCFF_X63_Y4_N29 3 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 1.899 ns; Loc. = LCFF_X63_Y4_N29; Fanout = 3; REG Node = 'AUTOLED:U2\|\\T:LIG\[5\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { AUTOLED:U2|LIG~631 AUTOLED:U2|\T:LIG[5] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.821 ns ( 43.23 % ) " "Info: Total cell delay = 0.821 ns ( 43.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.078 ns ( 56.77 % ) " "Info: Total interconnect delay = 1.078 ns ( 56.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.899 ns" { AUTOLED:U2|\T:LIG[0] AUTOLED:U2|Equal1~41 AUTOLED:U2|Equal1~42 AUTOLED:U2|LIG~631 AUTOLED:U2|\T:LIG[5] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "1.899 ns" { AUTOLED:U2|\T:LIG[0] {} AUTOLED:U2|Equal1~41 {} AUTOLED:U2|Equal1~42 {} AUTOLED:U2|LIG~631 {} AUTOLED:U2|\T:LIG[5] {} } { 0.000ns 0.339ns 0.261ns 0.478ns 0.000ns } { 0.000ns 0.438ns 0.149ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.695 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.695 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.537 ns) 2.695 ns AUTOLED:U2\|\\T:LIG\[5\] 3 REG LCFF_X63_Y4_N29 3 " "Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X63_Y4_N29; Fanout = 3; REG Node = 'AUTOLED:U2\|\\T:LIG\[5\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { CLK~clkctrl AUTOLED:U2|\T:LIG[5] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.99 % ) " "Info: Total cell delay = 1.536 ns ( 56.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.159 ns ( 43.01 % ) " "Info: Total interconnect delay = 1.159 ns ( 43.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:LIG[5] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:LIG[5] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.695 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.695 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.537 ns) 2.695 ns AUTOLED:U2\|\\T:LIG\[0\] 3 REG LCFF_X63_Y4_N25 2 " "Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X63_Y4_N25; Fanout = 2; REG Node = 'AUTOLED:U2\|\\T:LIG\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { CLK~clkctrl AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.99 % ) " "Info: Total cell delay = 1.536 ns ( 56.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.159 ns ( 43.01 % ) " "Info: Total interconnect delay = 1.159 ns ( 43.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:LIG[0] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:LIG[5] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:LIG[5] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:LIG[0] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.899 ns" { AUTOLED:U2|\T:LIG[0] AUTOLED:U2|Equal1~41 AUTOLED:U2|Equal1~42 AUTOLED:U2|LIG~631 AUTOLED:U2|\T:LIG[5] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "1.899 ns" { AUTOLED:U2|\T:LIG[0] {} AUTOLED:U2|Equal1~41 {} AUTOLED:U2|Equal1~42 {} AUTOLED:U2|LIG~631 {} AUTOLED:U2|\T:LIG[5] {} } { 0.000ns 0.339ns 0.261ns 0.478ns 0.000ns } { 0.000ns 0.438ns 0.149ns 0.150ns 0.084ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:LIG[5] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:LIG[5] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:LIG[0] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUTOLED:U2|\T:LIG[5] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { AUTOLED:U2|\T:LIG[5] {} } {  } {  } "" } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "AUTOLED:U2\|\\T:LIG\[0\] STATUS\[0\] CLK 6.348 ns register " "Info: tsu for register \"AUTOLED:U2\|\\T:LIG\[0\]\" (data pin = \"STATUS\[0\]\", clock pin = \"CLK\") is 6.348 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.079 ns + Longest pin register " "Info: + Longest pin to register delay is 9.079 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns STATUS\[0\] 1 PIN PIN_V2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 5; PIN Node = 'STATUS\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { STATUS[0] } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.464 ns) + CELL(0.393 ns) 7.709 ns AUTOLED:U2\|Equal0~36 2 COMB LCCOMB_X63_Y4_N14 5 " "Info: 2: + IC(6.464 ns) + CELL(0.393 ns) = 7.709 ns; Loc. = LCCOMB_X63_Y4_N14; Fanout = 5; COMB Node = 'AUTOLED:U2\|Equal0~36'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.857 ns" { STATUS[0] AUTOLED:U2|Equal0~36 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.438 ns) 8.587 ns AUTOLED:U2\|LIG~626 3 COMB LCCOMB_X63_Y4_N12 2 " "Info: 3: + IC(0.440 ns) + CELL(0.438 ns) = 8.587 ns; Loc. = LCCOMB_X63_Y4_N12; Fanout = 2; COMB Node = 'AUTOLED:U2\|LIG~626'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.878 ns" { AUTOLED:U2|Equal0~36 AUTOLED:U2|LIG~626 } "NODE_NAME" } } { "AUTOLED.vhd" "" { Text "D:/AUTOLED/AUTOLED.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.259 ns) + CELL(0.149 ns) 8.995 ns AUTOLED:U2\|LIG~627 4 COMB LCCOMB_X63_Y4_N24 1 " "Info: 4: + IC(0.259 ns) + CELL(0.149 ns) = 8.995 ns; Loc. = LCCOMB_X63_Y4_N24; Fanout = 1; COMB Node = 'AUTOLED:U2\|LIG~627'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.408 ns" { AUTOLED:U2|LIG~626 AUTOLED:U2|LIG~627 } "NODE_NAME" } } { "AUTOLED.vhd" "" { Text "D:/AUTOLED/AUTOLED.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 9.079 ns AUTOLED:U2\|\\T:LIG\[0\] 5 REG LCFF_X63_Y4_N25 2 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 9.079 ns; Loc. = LCFF_X63_Y4_N25; Fanout = 2; REG Node = 'AUTOLED:U2\|\\T:LIG\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { AUTOLED:U2|LIG~627 AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.916 ns ( 21.10 % ) " "Info: Total cell delay = 1.916 ns ( 21.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.163 ns ( 78.90 % ) " "Info: Total interconnect delay = 7.163 ns ( 78.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.079 ns" { STATUS[0] AUTOLED:U2|Equal0~36 AUTOLED:U2|LIG~626 AUTOLED:U2|LIG~627 AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "9.079 ns" { STATUS[0] {} STATUS[0]~combout {} AUTOLED:U2|Equal0~36 {} AUTOLED:U2|LIG~626 {} AUTOLED:U2|LIG~627 {} AUTOLED:U2|\T:LIG[0] {} } { 0.000ns 0.000ns 6.464ns 0.440ns 0.259ns 0.000ns } { 0.000ns 0.852ns 0.393ns 0.438ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.695 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.695 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.537 ns) 2.695 ns AUTOLED:U2\|\\T:LIG\[0\] 3 REG LCFF_X63_Y4_N25 2 " "Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X63_Y4_N25; Fanout = 2; REG Node = 'AUTOLED:U2\|\\T:LIG\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { CLK~clkctrl AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.99 % ) " "Info: Total cell delay = 1.536 ns ( 56.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.159 ns ( 43.01 % ) " "Info: Total interconnect delay = 1.159 ns ( 43.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:LIG[0] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.079 ns" { STATUS[0] AUTOLED:U2|Equal0~36 AUTOLED:U2|LIG~626 AUTOLED:U2|LIG~627 AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "9.079 ns" { STATUS[0] {} STATUS[0]~combout {} AUTOLED:U2|Equal0~36 {} AUTOLED:U2|LIG~626 {} AUTOLED:U2|LIG~627 {} AUTOLED:U2|\T:LIG[0] {} } { 0.000ns 0.000ns 6.464ns 0.440ns 0.259ns 0.000ns } { 0.000ns 0.852ns 0.393ns 0.438ns 0.149ns 0.084ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:LIG[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:LIG[0] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK LED\[4\] AUTOLED:U2\|\\T:LIG\[4\] 6.705 ns register " "Info: tco from clock \"CLK\" to destination pin \"LED\[4\]\" through register \"AUTOLED:U2\|\\T:LIG\[4\]\" is 6.705 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.695 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.695 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.537 ns) 2.695 ns AUTOLED:U2\|\\T:LIG\[4\] 3 REG LCFF_X63_Y4_N3 3 " "Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X63_Y4_N3; Fanout = 3; REG Node = 'AUTOLED:U2\|\\T:LIG\[4\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { CLK~clkctrl AUTOLED:U2|\T:LIG[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.99 % ) " "Info: Total cell delay = 1.536 ns ( 56.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.159 ns ( 43.01 % ) " "Info: Total interconnect delay = 1.159 ns ( 43.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:LIG[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:LIG[4] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.760 ns + Longest register pin " "Info: + Longest register to pin delay is 3.760 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AUTOLED:U2\|\\T:LIG\[4\] 1 REG LCFF_X63_Y4_N3 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y4_N3; Fanout = 3; REG Node = 'AUTOLED:U2\|\\T:LIG\[4\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUTOLED:U2|\T:LIG[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.952 ns) + CELL(2.808 ns) 3.760 ns LED\[4\] 2 PIN PIN_AD22 0 " "Info: 2: + IC(0.952 ns) + CELL(2.808 ns) = 3.760 ns; Loc. = PIN_AD22; Fanout = 0; PIN Node = 'LED\[4\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.760 ns" { AUTOLED:U2|\T:LIG[4] LED[4] } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.808 ns ( 74.68 % ) " "Info: Total cell delay = 2.808 ns ( 74.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.952 ns ( 25.32 % ) " "Info: Total interconnect delay = 0.952 ns ( 25.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.760 ns" { AUTOLED:U2|\T:LIG[4] LED[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.760 ns" { AUTOLED:U2|\T:LIG[4] {} LED[4] {} } { 0.000ns 0.952ns } { 0.000ns 2.808ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:LIG[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:LIG[4] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.760 ns" { AUTOLED:U2|\T:LIG[4] LED[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.760 ns" { AUTOLED:U2|\T:LIG[4] {} LED[4] {} } { 0.000ns 0.952ns } { 0.000ns 2.808ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "AUTOLED:U2\|\\T:COUNT\[0\] STATUS\[1\] CLK -4.221 ns register " "Info: th for register \"AUTOLED:U2\|\\T:COUNT\[0\]\" (data pin = \"STATUS\[1\]\", clock pin = \"CLK\") is -4.221 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.695 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.695 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.041 ns) + CELL(0.537 ns) 2.695 ns AUTOLED:U2\|\\T:COUNT\[0\] 3 REG LCFF_X63_Y4_N31 4 " "Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X63_Y4_N31; Fanout = 4; REG Node = 'AUTOLED:U2\|\\T:COUNT\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { CLK~clkctrl AUTOLED:U2|\T:COUNT[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.99 % ) " "Info: Total cell delay = 1.536 ns ( 56.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.159 ns ( 43.01 % ) " "Info: Total interconnect delay = 1.159 ns ( 43.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:COUNT[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:COUNT[0] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } {  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.182 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.182 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns STATUS\[1\] 1 PIN PIN_P23 5 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P23; Fanout = 5; PIN Node = 'STATUS\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { STATUS[1] } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.541 ns) + CELL(0.275 ns) 6.658 ns AUTOLED:U2\|Equal3~41 2 COMB LCCOMB_X63_Y4_N26 5 " "Info: 2: + IC(5.541 ns) + CELL(0.275 ns) = 6.658 ns; Loc. = LCCOMB_X63_Y4_N26; Fanout = 5; COMB Node = 'AUTOLED:U2\|Equal3~41'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.816 ns" { STATUS[1] AUTOLED:U2|Equal3~41 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.150 ns) 7.098 ns AUTOLED:U2\|COUNT~144 3 COMB LCCOMB_X63_Y4_N30 1 " "Info: 3: + IC(0.290 ns) + CELL(0.150 ns) = 7.098 ns; Loc. = LCCOMB_X63_Y4_N30; Fanout = 1; COMB Node = 'AUTOLED:U2\|COUNT~144'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.440 ns" { AUTOLED:U2|Equal3~41 AUTOLED:U2|COUNT~144 } "NODE_NAME" } } { "AUTOLED.vhd" "" { Text "D:/AUTOLED/AUTOLED.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 7.182 ns AUTOLED:U2\|\\T:COUNT\[0\] 4 REG LCFF_X63_Y4_N31 4 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 7.182 ns; Loc. = LCFF_X63_Y4_N31; Fanout = 4; REG Node = 'AUTOLED:U2\|\\T:COUNT\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { AUTOLED:U2|COUNT~144 AUTOLED:U2|\T:COUNT[0] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.351 ns ( 18.81 % ) " "Info: Total cell delay = 1.351 ns ( 18.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.831 ns ( 81.19 % ) " "Info: Total interconnect delay = 5.831 ns ( 81.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.182 ns" { STATUS[1] AUTOLED:U2|Equal3~41 AUTOLED:U2|COUNT~144 AUTOLED:U2|\T:COUNT[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "7.182 ns" { STATUS[1] {} STATUS[1]~combout {} AUTOLED:U2|Equal3~41 {} AUTOLED:U2|COUNT~144 {} AUTOLED:U2|\T:COUNT[0] {} } { 0.000ns 0.000ns 5.541ns 0.290ns 0.000ns } { 0.000ns 0.842ns 0.275ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { CLK CLK~clkctrl AUTOLED:U2|\T:COUNT[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { CLK {} CLK~combout {} CLK~clkctrl {} AUTOLED:U2|\T:COUNT[0] {} } { 0.000ns 0.000ns 0.118ns 1.041ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.182 ns" { STATUS[1] AUTOLED:U2|Equal3~41 AUTOLED:U2|COUNT~144 AUTOLED:U2|\T:COUNT[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "7.182 ns" { STATUS[1] {} STATUS[1]~combout {} AUTOLED:U2|Equal3~41 {} AUTOLED:U2|COUNT~144 {} AUTOLED:U2|\T:COUNT[0] {} } { 0.000ns 0.000ns 5.541ns 0.290ns 0.000ns } { 0.000ns 0.842ns 0.275ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}