prev_cmp_autoled.tan.qmsg

共6个尾灯

{ "Info" "ITDB_TSU_RESULT" "AUTOLED:U2\|\\T:LIG\[1\] STATUS\[0\] CLK 2.195 ns register " "Info: tsu for register \"AUTOLED:U2\|\\T:LIG\[1\]\" (data pin = \"STATUS\[0\]\", clock pin = \"CLK\") is 2.195 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.082 ns + Longest pin register " "Info: + Longest pin to register delay is 9.082 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns STATUS\[0\] 1 PIN PIN_V2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 5; PIN Node = 'STATUS\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { STATUS[0] } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.465 ns) + CELL(0.371 ns) 7.688 ns AUTOLED:U2\|Equal5~43 2 COMB LCCOMB_X63_Y4_N12 5 " "Info: 2: + IC(6.465 ns) + CELL(0.371 ns) = 7.688 ns; Loc. = LCCOMB_X63_Y4_N12; Fanout = 5; COMB Node = 'AUTOLED:U2\|Equal5~43'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.836 ns" { STATUS[0] AUTOLED:U2|Equal5~43 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.150 ns) 8.143 ns AUTOLED:U2\|LIG~628 3 COMB LCCOMB_X63_Y4_N30 1 " "Info: 3: + IC(0.305 ns) + CELL(0.150 ns) = 8.143 ns; Loc. = LCCOMB_X63_Y4_N30; Fanout = 1; COMB Node = 'AUTOLED:U2\|LIG~628'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.455 ns" { AUTOLED:U2|Equal5~43 AUTOLED:U2|LIG~628 } "NODE_NAME" } } { "AUTOLED.vhd" "" { Text "D:/AUTOLED/AUTOLED.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.417 ns) + CELL(0.438 ns) 8.998 ns AUTOLED:U2\|LIG~629 4 COMB LCCOMB_X63_Y4_N20 1 " "Info: 4: + IC(0.417 ns) + CELL(0.438 ns) = 8.998 ns; Loc. = LCCOMB_X63_Y4_N20; Fanout = 1; COMB Node = 'AUTOLED:U2\|LIG~629'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.855 ns" { AUTOLED:U2|LIG~628 AUTOLED:U2|LIG~629 } "NODE_NAME" } } { "AUTOLED.vhd" "" { Text "D:/AUTOLED/AUTOLED.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 9.082 ns AUTOLED:U2\|\\T:LIG\[1\] 5 REG LCFF_X63_Y4_N21 2 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 9.082 ns; Loc. = LCFF_X63_Y4_N21; Fanout = 2; REG Node = 'AUTOLED:U2\|\\T:LIG\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { AUTOLED:U2|LIG~629 AUTOLED:U2|\T:LIG[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.895 ns ( 20.87 % ) " "Info: Total cell delay = 1.895 ns ( 20.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.187 ns ( 79.13 % ) " "Info: Total interconnect delay = 7.187 ns ( 79.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.082 ns" { STATUS[0] AUTOLED:U2|Equal5~43 AUTOLED:U2|LIG~628 AUTOLED:U2|LIG~629 AUTOLED:U2|\T:LIG[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "9.082 ns" { STATUS[0] {} STATUS[0]~combout {} AUTOLED:U2|Equal5~43 {} AUTOLED:U2|LIG~628 {} AUTOLED:U2|LIG~629 {} AUTOLED:U2|\T:LIG[1] {} } { 0.000ns 0.000ns 6.465ns 0.305ns 0.417ns 0.000ns } { 0.000ns 0.852ns 0.371ns 0.150ns 0.438ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.851 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 6.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.794 ns) + CELL(0.787 ns) 3.580 ns DFRE:U1\|OC 2 REG LCFF_X34_Y13_N5 2 " "Info: 2: + IC(1.794 ns) + CELL(0.787 ns) = 3.580 ns; Loc. = LCFF_X34_Y13_N5; Fanout = 2; REG Node = 'DFRE:U1\|OC'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.581 ns" { CLK DFRE:U1|OC } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.706 ns) + CELL(0.000 ns) 5.286 ns DFRE:U1\|OC~clkctrl 3 COMB CLKCTRL_G13 8 " "Info: 3: + IC(1.706 ns) + CELL(0.000 ns) = 5.286 ns; Loc. = CLKCTRL_G13; Fanout = 8; COMB Node = 'DFRE:U1\|OC~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.706 ns" { DFRE:U1|OC DFRE:U1|OC~clkctrl } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 6.851 ns AUTOLED:U2\|\\T:LIG\[1\] 4 REG LCFF_X63_Y4_N21 2 " "Info: 4: + IC(1.028 ns) + CELL(0.537 ns) = 6.851 ns; Loc. = LCFF_X63_Y4_N21; Fanout = 2; REG Node = 'AUTOLED:U2\|\\T:LIG\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { DFRE:U1|OC~clkctrl AUTOLED:U2|\T:LIG[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 33.91 % ) " "Info: Total cell delay = 2.323 ns ( 33.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.528 ns ( 66.09 % ) " "Info: Total interconnect delay = 4.528 ns ( 66.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.851 ns" { CLK DFRE:U1|OC DFRE:U1|OC~clkctrl AUTOLED:U2|\T:LIG[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "6.851 ns" { CLK {} CLK~combout {} DFRE:U1|OC {} DFRE:U1|OC~clkctrl {} AUTOLED:U2|\T:LIG[1] {} } { 0.000ns 0.000ns 1.794ns 1.706ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.082 ns" { STATUS[0] AUTOLED:U2|Equal5~43 AUTOLED:U2|LIG~628 AUTOLED:U2|LIG~629 AUTOLED:U2|\T:LIG[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "9.082 ns" { STATUS[0] {} STATUS[0]~combout {} AUTOLED:U2|Equal5~43 {} AUTOLED:U2|LIG~628 {} AUTOLED:U2|LIG~629 {} AUTOLED:U2|\T:LIG[1] {} } { 0.000ns 0.000ns 6.465ns 0.305ns 0.417ns 0.000ns } { 0.000ns 0.852ns 0.371ns 0.150ns 0.438ns 0.084ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.851 ns" { CLK DFRE:U1|OC DFRE:U1|OC~clkctrl AUTOLED:U2|\T:LIG[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "6.851 ns" { CLK {} CLK~combout {} DFRE:U1|OC {} DFRE:U1|OC~clkctrl {} AUTOLED:U2|\T:LIG[1] {} } { 0.000ns 0.000ns 1.794ns 1.706ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK LED\[1\] AUTOLED:U2\|\\T:LIG\[1\] 10.837 ns register " "Info: tco from clock \"CLK\" to destination pin \"LED\[1\]\" through register \"AUTOLED:U2\|\\T:LIG\[1\]\" is 10.837 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.851 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 6.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.794 ns) + CELL(0.787 ns) 3.580 ns DFRE:U1\|OC 2 REG LCFF_X34_Y13_N5 2 " "Info: 2: + IC(1.794 ns) + CELL(0.787 ns) = 3.580 ns; Loc. = LCFF_X34_Y13_N5; Fanout = 2; REG Node = 'DFRE:U1\|OC'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.581 ns" { CLK DFRE:U1|OC } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.706 ns) + CELL(0.000 ns) 5.286 ns DFRE:U1\|OC~clkctrl 3 COMB CLKCTRL_G13 8 " "Info: 3: + IC(1.706 ns) + CELL(0.000 ns) = 5.286 ns; Loc. = CLKCTRL_G13; Fanout = 8; COMB Node = 'DFRE:U1\|OC~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.706 ns" { DFRE:U1|OC DFRE:U1|OC~clkctrl } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 6.851 ns AUTOLED:U2\|\\T:LIG\[1\] 4 REG LCFF_X63_Y4_N21 2 " "Info: 4: + IC(1.028 ns) + CELL(0.537 ns) = 6.851 ns; Loc. = LCFF_X63_Y4_N21; Fanout = 2; REG Node = 'AUTOLED:U2\|\\T:LIG\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { DFRE:U1|OC~clkctrl AUTOLED:U2|\T:LIG[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 33.91 % ) " "Info: Total cell delay = 2.323 ns ( 33.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.528 ns ( 66.09 % ) " "Info: Total interconnect delay = 4.528 ns ( 66.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.851 ns" { CLK DFRE:U1|OC DFRE:U1|OC~clkctrl AUTOLED:U2|\T:LIG[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "6.851 ns" { CLK {} CLK~combout {} DFRE:U1|OC {} DFRE:U1|OC~clkctrl {} AUTOLED:U2|\T:LIG[1] {} } { 0.000ns 0.000ns 1.794ns 1.706ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.736 ns + Longest register pin " "Info: + Longest register to pin delay is 3.736 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AUTOLED:U2\|\\T:LIG\[1\] 1 REG LCFF_X63_Y4_N21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y4_N21; Fanout = 2; REG Node = 'AUTOLED:U2\|\\T:LIG\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUTOLED:U2|\T:LIG[1] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(2.818 ns) 3.736 ns LED\[1\] 2 PIN PIN_AF23 0 " "Info: 2: + IC(0.918 ns) + CELL(2.818 ns) = 3.736 ns; Loc. = PIN_AF23; Fanout = 0; PIN Node = 'LED\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.736 ns" { AUTOLED:U2|\T:LIG[1] LED[1] } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.818 ns ( 75.43 % ) " "Info: Total cell delay = 2.818 ns ( 75.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.918 ns ( 24.57 % ) " "Info: Total interconnect delay = 0.918 ns ( 24.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.736 ns" { AUTOLED:U2|\T:LIG[1] LED[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.736 ns" { AUTOLED:U2|\T:LIG[1] {} LED[1] {} } { 0.000ns 0.918ns } { 0.000ns 2.818ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.851 ns" { CLK DFRE:U1|OC DFRE:U1|OC~clkctrl AUTOLED:U2|\T:LIG[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "6.851 ns" { CLK {} CLK~combout {} DFRE:U1|OC {} DFRE:U1|OC~clkctrl {} AUTOLED:U2|\T:LIG[1] {} } { 0.000ns 0.000ns 1.794ns 1.706ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.736 ns" { AUTOLED:U2|\T:LIG[1] LED[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.736 ns" { AUTOLED:U2|\T:LIG[1] {} LED[1] {} } { 0.000ns 0.918ns } { 0.000ns 2.818ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "AUTOLED:U2\|\\T:LIG\[4\] STATUS\[1\] CLK -0.069 ns register " "Info: th for register \"AUTOLED:U2\|\\T:LIG\[4\]\" (data pin = \"STATUS\[1\]\", clock pin = \"CLK\") is -0.069 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.851 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 6.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.794 ns) + CELL(0.787 ns) 3.580 ns DFRE:U1\|OC 2 REG LCFF_X34_Y13_N5 2 " "Info: 2: + IC(1.794 ns) + CELL(0.787 ns) = 3.580 ns; Loc. = LCFF_X34_Y13_N5; Fanout = 2; REG Node = 'DFRE:U1\|OC'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.581 ns" { CLK DFRE:U1|OC } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.706 ns) + CELL(0.000 ns) 5.286 ns DFRE:U1\|OC~clkctrl 3 COMB CLKCTRL_G13 8 " "Info: 3: + IC(1.706 ns) + CELL(0.000 ns) = 5.286 ns; Loc. = CLKCTRL_G13; Fanout = 8; COMB Node = 'DFRE:U1\|OC~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.706 ns" { DFRE:U1|OC DFRE:U1|OC~clkctrl } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 6.851 ns AUTOLED:U2\|\\T:LIG\[4\] 4 REG LCFF_X63_Y4_N29 3 " "Info: 4: + IC(1.028 ns) + CELL(0.537 ns) = 6.851 ns; Loc. = LCFF_X63_Y4_N29; Fanout = 3; REG Node = 'AUTOLED:U2\|\\T:LIG\[4\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { DFRE:U1|OC~clkctrl AUTOLED:U2|\T:LIG[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 33.91 % ) " "Info: Total cell delay = 2.323 ns ( 33.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.528 ns ( 66.09 % ) " "Info: Total interconnect delay = 4.528 ns ( 66.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.851 ns" { CLK DFRE:U1|OC DFRE:U1|OC~clkctrl AUTOLED:U2|\T:LIG[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "6.851 ns" { CLK {} CLK~combout {} DFRE:U1|OC {} DFRE:U1|OC~clkctrl {} AUTOLED:U2|\T:LIG[4] {} } { 0.000ns 0.000ns 1.794ns 1.706ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } {  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.186 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.186 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.842 ns) 0.842 ns STATUS\[1\] 1 PIN PIN_P23 5 " "Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P23; Fanout = 5; PIN Node = 'STATUS\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { STATUS[1] } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.540 ns) + CELL(0.275 ns) 6.657 ns AUTOLED:U2\|Equal2~61 2 COMB LCCOMB_X63_Y4_N18 6 " "Info: 2: + IC(5.540 ns) + CELL(0.275 ns) = 6.657 ns; Loc. = LCCOMB_X63_Y4_N18; Fanout = 6; COMB Node = 'AUTOLED:U2\|Equal2~61'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.815 ns" { STATUS[1] AUTOLED:U2|Equal2~61 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.295 ns) + CELL(0.150 ns) 7.102 ns AUTOLED:U2\|\\T:LIG\[4\]~2 3 COMB LCCOMB_X63_Y4_N28 1 " "Info: 3: + IC(0.295 ns) + CELL(0.150 ns) = 7.102 ns; Loc. = LCCOMB_X63_Y4_N28; Fanout = 1; COMB Node = 'AUTOLED:U2\|\\T:LIG\[4\]~2'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.445 ns" { AUTOLED:U2|Equal2~61 AUTOLED:U2|\T:LIG[4]~2 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 7.186 ns AUTOLED:U2\|\\T:LIG\[4\] 4 REG LCFF_X63_Y4_N29 3 " "Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 7.186 ns; Loc. = LCFF_X63_Y4_N29; Fanout = 3; REG Node = 'AUTOLED:U2\|\\T:LIG\[4\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { AUTOLED:U2|\T:LIG[4]~2 AUTOLED:U2|\T:LIG[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.351 ns ( 18.80 % ) " "Info: Total cell delay = 1.351 ns ( 18.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.835 ns ( 81.20 % ) " "Info: Total interconnect delay = 5.835 ns ( 81.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.186 ns" { STATUS[1] AUTOLED:U2|Equal2~61 AUTOLED:U2|\T:LIG[4]~2 AUTOLED:U2|\T:LIG[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "7.186 ns" { STATUS[1] {} STATUS[1]~combout {} AUTOLED:U2|Equal2~61 {} AUTOLED:U2|\T:LIG[4]~2 {} AUTOLED:U2|\T:LIG[4] {} } { 0.000ns 0.000ns 5.540ns 0.295ns 0.000ns } { 0.000ns 0.842ns 0.275ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.851 ns" { CLK DFRE:U1|OC DFRE:U1|OC~clkctrl AUTOLED:U2|\T:LIG[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "6.851 ns" { CLK {} CLK~combout {} DFRE:U1|OC {} DFRE:U1|OC~clkctrl {} AUTOLED:U2|\T:LIG[4] {} } { 0.000ns 0.000ns 1.794ns 1.706ns 1.028ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.186 ns" { STATUS[1] AUTOLED:U2|Equal2~61 AUTOLED:U2|\T:LIG[4]~2 AUTOLED:U2|\T:LIG[4] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "7.186 ns" { STATUS[1] {} STATUS[1]~combout {} AUTOLED:U2|Equal2~61 {} AUTOLED:U2|\T:LIG[4]~2 {} AUTOLED:U2|\T:LIG[4] {} } { 0.000ns 0.000ns 5.540ns 0.295ns 0.000ns } { 0.000ns 0.842ns 0.275ns 0.150ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}