📄 prev_cmp_autoled.tan.qmsg

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💻 QMSG
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "DFRE:U1\|OC " "Info: Detected ripple clock \"DFRE:U1\|OC\" as buffer" {  } { { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DFRE:U1\|OC" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register DFRE:U1\|fre\[0\] register DFRE:U1\|fre\[24\] 270.86 MHz 3.692 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 270.86 MHz between source register \"DFRE:U1\|fre\[0\]\" and destination register \"DFRE:U1\|fre\[24\]\" (period= 3.692 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.473 ns + Longest register register " "Info: + Longest register to register delay is 3.473 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DFRE:U1\|fre\[0\] 1 REG LCFF_X35_Y14_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y14_N1; Fanout = 3; REG Node = 'DFRE:U1\|fre\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DFRE:U1|fre[0] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.309 ns) + CELL(0.393 ns) 0.702 ns DFRE:U1\|Add0~313 2 COMB LCCOMB_X35_Y14_N6 2 " "Info: 2: + IC(0.309 ns) + CELL(0.393 ns) = 0.702 ns; Loc. = LCCOMB_X35_Y14_N6; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~313'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.702 ns" { DFRE:U1|fre[0] DFRE:U1|Add0~313 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.773 ns DFRE:U1\|Add0~315 3 COMB LCCOMB_X35_Y14_N8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.773 ns; Loc. = LCCOMB_X35_Y14_N8; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~315'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~313 DFRE:U1|Add0~315 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.844 ns DFRE:U1\|Add0~317 4 COMB LCCOMB_X35_Y14_N10 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.844 ns; Loc. = LCCOMB_X35_Y14_N10; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~317'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~315 DFRE:U1|Add0~317 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.915 ns DFRE:U1\|Add0~319 5 COMB LCCOMB_X35_Y14_N12 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 0.915 ns; Loc. = LCCOMB_X35_Y14_N12; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~319'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~317 DFRE:U1|Add0~319 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.074 ns DFRE:U1\|Add0~321 6 COMB LCCOMB_X35_Y14_N14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.159 ns) = 1.074 ns; Loc. = LCCOMB_X35_Y14_N14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~321'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { DFRE:U1|Add0~319 DFRE:U1|Add0~321 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.145 ns DFRE:U1\|Add0~323 7 COMB LCCOMB_X35_Y14_N16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.145 ns; Loc. = LCCOMB_X35_Y14_N16; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~323'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~321 DFRE:U1|Add0~323 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.216 ns DFRE:U1\|Add0~325 8 COMB LCCOMB_X35_Y14_N18 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.216 ns; Loc. = LCCOMB_X35_Y14_N18; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~325'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~323 DFRE:U1|Add0~325 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.287 ns DFRE:U1\|Add0~327 9 COMB LCCOMB_X35_Y14_N20 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.287 ns; Loc. = LCCOMB_X35_Y14_N20; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~327'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~325 DFRE:U1|Add0~327 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.358 ns DFRE:U1\|Add0~329 10 COMB LCCOMB_X35_Y14_N22 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.358 ns; Loc. = LCCOMB_X35_Y14_N22; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~329'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~327 DFRE:U1|Add0~329 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.429 ns DFRE:U1\|Add0~331 11 COMB LCCOMB_X35_Y14_N24 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.429 ns; Loc. = LCCOMB_X35_Y14_N24; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~331'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~329 DFRE:U1|Add0~331 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.500 ns DFRE:U1\|Add0~333 12 COMB LCCOMB_X35_Y14_N26 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.500 ns; Loc. = LCCOMB_X35_Y14_N26; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~333'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~331 DFRE:U1|Add0~333 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.571 ns DFRE:U1\|Add0~335 13 COMB LCCOMB_X35_Y14_N28 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.571 ns; Loc. = LCCOMB_X35_Y14_N28; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~335'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~333 DFRE:U1|Add0~335 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 1.717 ns DFRE:U1\|Add0~337 14 COMB LCCOMB_X35_Y14_N30 2 " "Info: 14: + IC(0.000 ns) + CELL(0.146 ns) = 1.717 ns; Loc. = LCCOMB_X35_Y14_N30; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~337'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.146 ns" { DFRE:U1|Add0~335 DFRE:U1|Add0~337 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.788 ns DFRE:U1\|Add0~339 15 COMB LCCOMB_X35_Y13_N0 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.788 ns; Loc. = LCCOMB_X35_Y13_N0; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~339'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~337 DFRE:U1|Add0~339 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.859 ns DFRE:U1\|Add0~341 16 COMB LCCOMB_X35_Y13_N2 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 1.859 ns; Loc. = LCCOMB_X35_Y13_N2; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~341'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~339 DFRE:U1|Add0~341 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.930 ns DFRE:U1\|Add0~343 17 COMB LCCOMB_X35_Y13_N4 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 1.930 ns; Loc. = LCCOMB_X35_Y13_N4; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~343'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~341 DFRE:U1|Add0~343 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.001 ns DFRE:U1\|Add0~345 18 COMB LCCOMB_X35_Y13_N6 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.001 ns; Loc. = LCCOMB_X35_Y13_N6; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~345'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~343 DFRE:U1|Add0~345 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.072 ns DFRE:U1\|Add0~347 19 COMB LCCOMB_X35_Y13_N8 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 2.072 ns; Loc. = LCCOMB_X35_Y13_N8; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~347'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~345 DFRE:U1|Add0~347 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.143 ns DFRE:U1\|Add0~349 20 COMB LCCOMB_X35_Y13_N10 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.143 ns; Loc. = LCCOMB_X35_Y13_N10; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~349'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~347 DFRE:U1|Add0~349 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.214 ns DFRE:U1\|Add0~351 21 COMB LCCOMB_X35_Y13_N12 2 " "Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 2.214 ns; Loc. = LCCOMB_X35_Y13_N12; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~351'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~349 DFRE:U1|Add0~351 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 2.373 ns DFRE:U1\|Add0~353 22 COMB LCCOMB_X35_Y13_N14 2 " "Info: 22: + IC(0.000 ns) + CELL(0.159 ns) = 2.373 ns; Loc. = LCCOMB_X35_Y13_N14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~353'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { DFRE:U1|Add0~351 DFRE:U1|Add0~353 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.444 ns DFRE:U1\|Add0~355 23 COMB LCCOMB_X35_Y13_N16 2 " "Info: 23: + IC(0.000 ns) + CELL(0.071 ns) = 2.444 ns; Loc. = LCCOMB_X35_Y13_N16; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~355'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~353 DFRE:U1|Add0~355 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.515 ns DFRE:U1\|Add0~357 24 COMB LCCOMB_X35_Y13_N18 2 " "Info: 24: + IC(0.000 ns) + CELL(0.071 ns) = 2.515 ns; Loc. = LCCOMB_X35_Y13_N18; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~357'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~355 DFRE:U1|Add0~357 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.586 ns DFRE:U1\|Add0~359 25 COMB LCCOMB_X35_Y13_N20 2 " "Info: 25: + IC(0.000 ns) + CELL(0.071 ns) = 2.586 ns; Loc. = LCCOMB_X35_Y13_N20; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~359'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~357 DFRE:U1|Add0~359 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 2.996 ns DFRE:U1\|Add0~360 26 COMB LCCOMB_X35_Y13_N22 1 " "Info: 26: + IC(0.000 ns) + CELL(0.410 ns) = 2.996 ns; Loc. = LCCOMB_X35_Y13_N22; Fanout = 1; COMB Node = 'DFRE:U1\|Add0~360'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DFRE:U1|Add0~359 DFRE:U1|Add0~360 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.243 ns) + CELL(0.150 ns) 3.389 ns DFRE:U1\|fre~248 27 COMB LCCOMB_X35_Y13_N30 1 " "Info: 27: + IC(0.243 ns) + CELL(0.150 ns) = 3.389 ns; Loc. = LCCOMB_X35_Y13_N30; Fanout = 1; COMB Node = 'DFRE:U1\|fre~248'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.393 ns" { DFRE:U1|Add0~360 DFRE:U1|fre~248 } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.473 ns DFRE:U1\|fre\[24\] 28 REG LCFF_X35_Y13_N31 3 " "Info: 28: + IC(0.000 ns) + CELL(0.084 ns) = 3.473 ns; Loc. = LCFF_X35_Y13_N31; Fanout = 3; REG Node = 'DFRE:U1\|fre\[24\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { DFRE:U1|fre~248 DFRE:U1|fre[24] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.921 ns ( 84.11 % ) " "Info: Total cell delay = 2.921 ns ( 84.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.552 ns ( 15.89 % ) " "Info: Total interconnect delay = 0.552 ns ( 15.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.473 ns" { DFRE:U1|fre[0] DFRE:U1|Add0~313 DFRE:U1|Add0~315 DFRE:U1|Add0~317 DFRE:U1|Add0~319 DFRE:U1|Add0~321 DFRE:U1|Add0~323 DFRE:U1|Add0~325 DFRE:U1|Add0~327 DFRE:U1|Add0~329 DFRE:U1|Add0~331 DFRE:U1|Add0~333 DFRE:U1|Add0~335 DFRE:U1|Add0~337 DFRE:U1|Add0~339 DFRE:U1|Add0~341 DFRE:U1|Add0~343 DFRE:U1|Add0~345 DFRE:U1|Add0~347 DFRE:U1|Add0~349 DFRE:U1|Add0~351 DFRE:U1|Add0~353 DFRE:U1|Add0~355 DFRE:U1|Add0~357 DFRE:U1|Add0~359 DFRE:U1|Add0~360 DFRE:U1|fre~248 DFRE:U1|fre[24] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.473 ns" { DFRE:U1|fre[0] {} DFRE:U1|Add0~313 {} DFRE:U1|Add0~315 {} DFRE:U1|Add0~317 {} DFRE:U1|Add0~319 {} DFRE:U1|Add0~321 {} DFRE:U1|Add0~323 {} DFRE:U1|Add0~325 {} DFRE:U1|Add0~327 {} DFRE:U1|Add0~329 {} DFRE:U1|Add0~331 {} DFRE:U1|Add0~333 {} DFRE:U1|Add0~335 {} DFRE:U1|Add0~337 {} DFRE:U1|Add0~339 {} DFRE:U1|Add0~341 {} DFRE:U1|Add0~343 {} DFRE:U1|Add0~345 {} DFRE:U1|Add0~347 {} DFRE:U1|Add0~349 {} DFRE:U1|Add0~351 {} DFRE:U1|Add0~353 {} DFRE:U1|Add0~355 {} DFRE:U1|Add0~357 {} DFRE:U1|Add0~359 {} DFRE:U1|Add0~360 {} DFRE:U1|fre~248 {} DFRE:U1|fre[24] {} } { 0.000ns 0.309ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.243ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.005 ns - Smallest " "Info: - Smallest clock skew is -0.005 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.655 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.655 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'CLK~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.537 ns) 2.655 ns DFRE:U1\|fre\[24\] 3 REG LCFF_X35_Y13_N31 3 " "Info: 3: + IC(1.001 ns) + CELL(0.537 ns) = 2.655 ns; Loc. = LCFF_X35_Y13_N31; Fanout = 3; REG Node = 'DFRE:U1\|fre\[24\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.538 ns" { CLK~clkctrl DFRE:U1|fre[24] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.85 % ) " "Info: Total cell delay = 1.536 ns ( 57.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.119 ns ( 42.15 % ) " "Info: Total interconnect delay = 1.119 ns ( 42.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.655 ns" { CLK CLK~clkctrl DFRE:U1|fre[24] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.655 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DFRE:U1|fre[24] {} } { 0.000ns 0.000ns 0.118ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.660 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLK 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLK'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLK~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'CLK~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "TOP.vhd" "" { Text "D:/AUTOLED/TOP.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.006 ns) + CELL(0.537 ns) 2.660 ns DFRE:U1\|fre\[0\] 3 REG LCFF_X35_Y14_N1 3 " "Info: 3: + IC(1.006 ns) + CELL(0.537 ns) = 2.660 ns; Loc. = LCFF_X35_Y14_N1; Fanout = 3; REG Node = 'DFRE:U1\|fre\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.543 ns" { CLK~clkctrl DFRE:U1|fre[0] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.74 % ) " "Info: Total cell delay = 1.536 ns ( 57.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.124 ns ( 42.26 % ) " "Info: Total interconnect delay = 1.124 ns ( 42.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.660 ns" { CLK CLK~clkctrl DFRE:U1|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.660 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DFRE:U1|fre[0] {} } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.655 ns" { CLK CLK~clkctrl DFRE:U1|fre[24] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.655 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DFRE:U1|fre[24] {} } { 0.000ns 0.000ns 0.118ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.660 ns" { CLK CLK~clkctrl DFRE:U1|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.660 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DFRE:U1|fre[0] {} } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.473 ns" { DFRE:U1|fre[0] DFRE:U1|Add0~313 DFRE:U1|Add0~315 DFRE:U1|Add0~317 DFRE:U1|Add0~319 DFRE:U1|Add0~321 DFRE:U1|Add0~323 DFRE:U1|Add0~325 DFRE:U1|Add0~327 DFRE:U1|Add0~329 DFRE:U1|Add0~331 DFRE:U1|Add0~333 DFRE:U1|Add0~335 DFRE:U1|Add0~337 DFRE:U1|Add0~339 DFRE:U1|Add0~341 DFRE:U1|Add0~343 DFRE:U1|Add0~345 DFRE:U1|Add0~347 DFRE:U1|Add0~349 DFRE:U1|Add0~351 DFRE:U1|Add0~353 DFRE:U1|Add0~355 DFRE:U1|Add0~357 DFRE:U1|Add0~359 DFRE:U1|Add0~360 DFRE:U1|fre~248 DFRE:U1|fre[24] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.473 ns" { DFRE:U1|fre[0] {} DFRE:U1|Add0~313 {} DFRE:U1|Add0~315 {} DFRE:U1|Add0~317 {} DFRE:U1|Add0~319 {} DFRE:U1|Add0~321 {} DFRE:U1|Add0~323 {} DFRE:U1|Add0~325 {} DFRE:U1|Add0~327 {} DFRE:U1|Add0~329 {} DFRE:U1|Add0~331 {} DFRE:U1|Add0~333 {} DFRE:U1|Add0~335 {} DFRE:U1|Add0~337 {} DFRE:U1|Add0~339 {} DFRE:U1|Add0~341 {} DFRE:U1|Add0~343 {} DFRE:U1|Add0~345 {} DFRE:U1|Add0~347 {} DFRE:U1|Add0~349 {} DFRE:U1|Add0~351 {} DFRE:U1|Add0~353 {} DFRE:U1|Add0~355 {} DFRE:U1|Add0~357 {} DFRE:U1|Add0~359 {} DFRE:U1|Add0~360 {} DFRE:U1|fre~248 {} DFRE:U1|fre[24] {} } { 0.000ns 0.309ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.243ns 0.000ns } { 0.000ns 0.393ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.410ns 0.150ns 0.084ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.655 ns" { CLK CLK~clkctrl DFRE:U1|fre[24] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.655 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DFRE:U1|fre[24] {} } { 0.000ns 0.000ns 0.118ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.660 ns" { CLK CLK~clkctrl DFRE:U1|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.660 ns" { CLK {} CLK~combout {} CLK~clkctrl {} DFRE:U1|fre[0] {} } { 0.000ns 0.000ns 0.118ns 1.006ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
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