prev_cmp_autoled.fit.qmsg

共6个尾灯

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "3.651 ns register register " "Info: Estimated most critical path is register to register delay of 3.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DFRE:U1\|fre\[0\] 1 REG LAB_X35_Y14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X35_Y14; Fanout = 3; REG Node = 'DFRE:U1\|fre\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DFRE:U1|fre[0] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.455 ns) + CELL(0.414 ns) 0.869 ns DFRE:U1\|Add0~313 2 COMB LAB_X35_Y14 2 " "Info: 2: + IC(0.455 ns) + CELL(0.414 ns) = 0.869 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~313'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.869 ns" { DFRE:U1|fre[0] DFRE:U1|Add0~313 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.940 ns DFRE:U1\|Add0~315 3 COMB LAB_X35_Y14 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.940 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~315'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~313 DFRE:U1|Add0~315 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.011 ns DFRE:U1\|Add0~317 4 COMB LAB_X35_Y14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.011 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~317'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~315 DFRE:U1|Add0~317 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.082 ns DFRE:U1\|Add0~319 5 COMB LAB_X35_Y14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.082 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~319'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~317 DFRE:U1|Add0~319 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.153 ns DFRE:U1\|Add0~321 6 COMB LAB_X35_Y14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.153 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~321'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~319 DFRE:U1|Add0~321 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.224 ns DFRE:U1\|Add0~323 7 COMB LAB_X35_Y14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.224 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~323'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~321 DFRE:U1|Add0~323 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.295 ns DFRE:U1\|Add0~325 8 COMB LAB_X35_Y14 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.295 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~325'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~323 DFRE:U1|Add0~325 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.366 ns DFRE:U1\|Add0~327 9 COMB LAB_X35_Y14 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.366 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~327'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~325 DFRE:U1|Add0~327 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.437 ns DFRE:U1\|Add0~329 10 COMB LAB_X35_Y14 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.437 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~329'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~327 DFRE:U1|Add0~329 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.508 ns DFRE:U1\|Add0~331 11 COMB LAB_X35_Y14 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.508 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~331'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~329 DFRE:U1|Add0~331 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.579 ns DFRE:U1\|Add0~333 12 COMB LAB_X35_Y14 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.579 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~333'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~331 DFRE:U1|Add0~333 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.650 ns DFRE:U1\|Add0~335 13 COMB LAB_X35_Y14 2 " "Info: 13: + IC(0.000 ns) + CELL(0.071 ns) = 1.650 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~335'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~333 DFRE:U1|Add0~335 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.721 ns DFRE:U1\|Add0~337 14 COMB LAB_X35_Y14 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.721 ns; Loc. = LAB_X35_Y14; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~337'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~335 DFRE:U1|Add0~337 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.090 ns) + CELL(0.071 ns) 1.882 ns DFRE:U1\|Add0~339 15 COMB LAB_X35_Y13 2 " "Info: 15: + IC(0.090 ns) + CELL(0.071 ns) = 1.882 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~339'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.161 ns" { DFRE:U1|Add0~337 DFRE:U1|Add0~339 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.953 ns DFRE:U1\|Add0~341 16 COMB LAB_X35_Y13 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 1.953 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~341'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~339 DFRE:U1|Add0~341 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.024 ns DFRE:U1\|Add0~343 17 COMB LAB_X35_Y13 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 2.024 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~343'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~341 DFRE:U1|Add0~343 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.095 ns DFRE:U1\|Add0~345 18 COMB LAB_X35_Y13 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.095 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~345'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~343 DFRE:U1|Add0~345 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.166 ns DFRE:U1\|Add0~347 19 COMB LAB_X35_Y13 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 2.166 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~347'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~345 DFRE:U1|Add0~347 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.237 ns DFRE:U1\|Add0~349 20 COMB LAB_X35_Y13 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.237 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~349'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~347 DFRE:U1|Add0~349 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.308 ns DFRE:U1\|Add0~351 21 COMB LAB_X35_Y13 2 " "Info: 21: + IC(0.000 ns) + CELL(0.071 ns) = 2.308 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~351'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~349 DFRE:U1|Add0~351 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.379 ns DFRE:U1\|Add0~353 22 COMB LAB_X35_Y13 2 " "Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 2.379 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~353'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~351 DFRE:U1|Add0~353 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.450 ns DFRE:U1\|Add0~355 23 COMB LAB_X35_Y13 2 " "Info: 23: + IC(0.000 ns) + CELL(0.071 ns) = 2.450 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~355'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~353 DFRE:U1|Add0~355 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.521 ns DFRE:U1\|Add0~357 24 COMB LAB_X35_Y13 2 " "Info: 24: + IC(0.000 ns) + CELL(0.071 ns) = 2.521 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~357'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~355 DFRE:U1|Add0~357 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.592 ns DFRE:U1\|Add0~359 25 COMB LAB_X35_Y13 2 " "Info: 25: + IC(0.000 ns) + CELL(0.071 ns) = 2.592 ns; Loc. = LAB_X35_Y13; Fanout = 2; COMB Node = 'DFRE:U1\|Add0~359'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { DFRE:U1|Add0~357 DFRE:U1|Add0~359 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.002 ns DFRE:U1\|Add0~360 26 COMB LAB_X35_Y13 1 " "Info: 26: + IC(0.000 ns) + CELL(0.410 ns) = 3.002 ns; Loc. = LAB_X35_Y13; Fanout = 1; COMB Node = 'DFRE:U1\|Add0~360'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { DFRE:U1|Add0~359 DFRE:U1|Add0~360 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 926 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 3.567 ns DFRE:U1\|fre~248 27 COMB LAB_X35_Y13 1 " "Info: 27: + IC(0.127 ns) + CELL(0.438 ns) = 3.567 ns; Loc. = LAB_X35_Y13; Fanout = 1; COMB Node = 'DFRE:U1\|fre~248'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { DFRE:U1|Add0~360 DFRE:U1|fre~248 } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.651 ns DFRE:U1\|fre\[24\] 28 REG LAB_X35_Y13 3 " "Info: 28: + IC(0.000 ns) + CELL(0.084 ns) = 3.651 ns; Loc. = LAB_X35_Y13; Fanout = 3; REG Node = 'DFRE:U1\|fre\[24\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { DFRE:U1|fre~248 DFRE:U1|fre[24] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/AUTOLED/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.979 ns ( 81.59 % ) " "Info: Total cell delay = 2.979 ns ( 81.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.672 ns ( 18.41 % ) " "Info: Total interconnect delay = 0.672 ns ( 18.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.651 ns" { DFRE:U1|fre[0] DFRE:U1|Add0~313 DFRE:U1|Add0~315 DFRE:U1|Add0~317 DFRE:U1|Add0~319 DFRE:U1|Add0~321 DFRE:U1|Add0~323 DFRE:U1|Add0~325 DFRE:U1|Add0~327 DFRE:U1|Add0~329 DFRE:U1|Add0~331 DFRE:U1|Add0~333 DFRE:U1|Add0~335 DFRE:U1|Add0~337 DFRE:U1|Add0~339 DFRE:U1|Add0~341 DFRE:U1|Add0~343 DFRE:U1|Add0~345 DFRE:U1|Add0~347 DFRE:U1|Add0~349 DFRE:U1|Add0~351 DFRE:U1|Add0~353 DFRE:U1|Add0~355 DFRE:U1|Add0~357 DFRE:U1|Add0~359 DFRE:U1|Add0~360 DFRE:U1|fre~248 DFRE:U1|fre[24] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X55_Y0 X65_Y11 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X55_Y0 to location X65_Y11" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "6 " "Warning: Found 6 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LED\[0\] 0 " "Info: Pin \"LED\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LED\[1\] 0 " "Info: Pin \"LED\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LED\[2\] 0 " "Info: Pin \"LED\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LED\[3\] 0 " "Info: Pin \"LED\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LED\[4\] 0 " "Info: Pin \"LED\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LED\[5\] 0 " "Info: Pin \"LED\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/AUTOLED/AUTOLED.fit.smsg " "Info: Generated suppressed messages file D:/AUTOLED/AUTOLED.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "200 " "Info: Allocated 200 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 13 15:09:54 2008 " "Info: Processing ended: Thu Nov 13 15:09:54 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}