autoled.tan.rpt

共6个尾灯

; N/A           ; None        ; -4.735 ns ; STATUS[1] ; AUTOLED:U2|\T:LIG[0]   ; CLK      ;
; N/A           ; None        ; -4.737 ns ; STATUS[1] ; AUTOLED:U2|\T:LIG[2]   ; CLK      ;
; N/A           ; None        ; -4.744 ns ; STATUS[2] ; AUTOLED:U2|\T:LIG[0]   ; CLK      ;
; N/A           ; None        ; -4.855 ns ; STATUS[2] ; AUTOLED:U2|\T:LIG[2]   ; CLK      ;
; N/A           ; None        ; -4.882 ns ; STATUS[3] ; AUTOLED:U2|\T:LIG[1]   ; CLK      ;
; N/A           ; None        ; -4.915 ns ; STATUS[3] ; AUTOLED:U2|\T:LIG[3]   ; CLK      ;
; N/A           ; None        ; -4.923 ns ; STATUS[3] ; AUTOLED:U2|\T:LIG[4]   ; CLK      ;
; N/A           ; None        ; -4.937 ns ; STATUS[3] ; AUTOLED:U2|\T:LIG[5]   ; CLK      ;
; N/A           ; None        ; -5.065 ns ; STATUS[3] ; AUTOLED:U2|\T:LIG[0]   ; CLK      ;
; N/A           ; None        ; -5.176 ns ; STATUS[3] ; AUTOLED:U2|\T:LIG[2]   ; CLK      ;
; N/A           ; None        ; -5.256 ns ; STATUS[0] ; AUTOLED:U2|\T:COUNT[0] ; CLK      ;
; N/A           ; None        ; -5.262 ns ; STATUS[0] ; AUTOLED:U2|\T:COUNT[1] ; CLK      ;
; N/A           ; None        ; -5.481 ns ; STATUS[0] ; AUTOLED:U2|\T:LIG[1]   ; CLK      ;
; N/A           ; None        ; -5.501 ns ; STATUS[0] ; AUTOLED:U2|\T:LIG[3]   ; CLK      ;
; N/A           ; None        ; -5.509 ns ; STATUS[0] ; AUTOLED:U2|\T:LIG[4]   ; CLK      ;
; N/A           ; None        ; -5.523 ns ; STATUS[0] ; AUTOLED:U2|\T:LIG[5]   ; CLK      ;
; N/A           ; None        ; -5.574 ns ; STATUS[0] ; AUTOLED:U2|\T:LIG[0]   ; CLK      ;
; N/A           ; None        ; -5.685 ns ; STATUS[0] ; AUTOLED:U2|\T:LIG[2]   ; CLK      ;
+---------------+-------------+-----------+-----------+------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Mon Nov 17 11:55:57 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off AUTOLED -c AUTOLED --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" Internal fmax is restricted to 420.17 MHz between source register "AUTOLED:U2|\T:LIG[0]" and destination register "AUTOLED:U2|\T:LIG[5]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.899 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y4_N25; Fanout = 2; REG Node = 'AUTOLED:U2|\T:LIG[0]'
            Info: 2: + IC(0.339 ns) + CELL(0.438 ns) = 0.777 ns; Loc. = LCCOMB_X63_Y4_N6; Fanout = 2; COMB Node = 'AUTOLED:U2|Equal1~41'
            Info: 3: + IC(0.261 ns) + CELL(0.149 ns) = 1.187 ns; Loc. = LCCOMB_X63_Y4_N16; Fanout = 4; COMB Node = 'AUTOLED:U2|Equal1~42'
            Info: 4: + IC(0.478 ns) + CELL(0.150 ns) = 1.815 ns; Loc. = LCCOMB_X63_Y4_N28; Fanout = 1; COMB Node = 'AUTOLED:U2|LIG~631'
            Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 1.899 ns; Loc. = LCFF_X63_Y4_N29; Fanout = 3; REG Node = 'AUTOLED:U2|\T:LIG[5]'
            Info: Total cell delay = 0.821 ns ( 43.23 % )
            Info: Total interconnect delay = 1.078 ns ( 56.77 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CLK" to destination register is 2.695 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X63_Y4_N29; Fanout = 3; REG Node = 'AUTOLED:U2|\T:LIG[5]'
                Info: Total cell delay = 1.536 ns ( 56.99 % )
                Info: Total interconnect delay = 1.159 ns ( 43.01 % )
            Info: - Longest clock path from clock "CLK" to source register is 2.695 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'
                Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X63_Y4_N25; Fanout = 2; REG Node = 'AUTOLED:U2|\T:LIG[0]'
                Info: Total cell delay = 1.536 ns ( 56.99 % )
                Info: Total interconnect delay = 1.159 ns ( 43.01 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "AUTOLED:U2|\T:LIG[0]" (data pin = "STATUS[0]", clock pin = "CLK") is 6.348 ns
    Info: + Longest pin to register delay is 9.079 ns
        Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 5; PIN Node = 'STATUS[0]'
        Info: 2: + IC(6.464 ns) + CELL(0.393 ns) = 7.709 ns; Loc. = LCCOMB_X63_Y4_N14; Fanout = 5; COMB Node = 'AUTOLED:U2|Equal0~36'
        Info: 3: + IC(0.440 ns) + CELL(0.438 ns) = 8.587 ns; Loc. = LCCOMB_X63_Y4_N12; Fanout = 2; COMB Node = 'AUTOLED:U2|LIG~626'
        Info: 4: + IC(0.259 ns) + CELL(0.149 ns) = 8.995 ns; Loc. = LCCOMB_X63_Y4_N24; Fanout = 1; COMB Node = 'AUTOLED:U2|LIG~627'
        Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 9.079 ns; Loc. = LCFF_X63_Y4_N25; Fanout = 2; REG Node = 'AUTOLED:U2|\T:LIG[0]'
        Info: Total cell delay = 1.916 ns ( 21.10 % )
        Info: Total interconnect delay = 7.163 ns ( 78.90 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.695 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X63_Y4_N25; Fanout = 2; REG Node = 'AUTOLED:U2|\T:LIG[0]'
        Info: Total cell delay = 1.536 ns ( 56.99 % )
        Info: Total interconnect delay = 1.159 ns ( 43.01 % )
Info: tco from clock "CLK" to destination pin "LED[4]" through register "AUTOLED:U2|\T:LIG[4]" is 6.705 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.695 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X63_Y4_N3; Fanout = 3; REG Node = 'AUTOLED:U2|\T:LIG[4]'
        Info: Total cell delay = 1.536 ns ( 56.99 % )
        Info: Total interconnect delay = 1.159 ns ( 43.01 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.760 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X63_Y4_N3; Fanout = 3; REG Node = 'AUTOLED:U2|\T:LIG[4]'
        Info: 2: + IC(0.952 ns) + CELL(2.808 ns) = 3.760 ns; Loc. = PIN_AD22; Fanout = 0; PIN Node = 'LED[4]'
        Info: Total cell delay = 2.808 ns ( 74.68 % )
        Info: Total interconnect delay = 0.952 ns ( 25.32 % )
Info: th for register "AUTOLED:U2|\T:COUNT[0]" (data pin = "STATUS[1]", clock pin = "CLK") is -4.221 ns
    Info: + Longest clock path from clock "CLK" to destination register is 2.695 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLK'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CLK~clkctrl'
        Info: 3: + IC(1.041 ns) + CELL(0.537 ns) = 2.695 ns; Loc. = LCFF_X63_Y4_N31; Fanout = 4; REG Node = 'AUTOLED:U2|\T:COUNT[0]'
        Info: Total cell delay = 1.536 ns ( 56.99 % )
        Info: Total interconnect delay = 1.159 ns ( 43.01 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 7.182 ns
        Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_P23; Fanout = 5; PIN Node = 'STATUS[1]'
        Info: 2: + IC(5.541 ns) + CELL(0.275 ns) = 6.658 ns; Loc. = LCCOMB_X63_Y4_N26; Fanout = 5; COMB Node = 'AUTOLED:U2|Equal3~41'
        Info: 3: + IC(0.290 ns) + CELL(0.150 ns) = 7.098 ns; Loc. = LCCOMB_X63_Y4_N30; Fanout = 1; COMB Node = 'AUTOLED:U2|COUNT~144'
        Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 7.182 ns; Loc. = LCFF_X63_Y4_N31; Fanout = 4; REG Node = 'AUTOLED:U2|\T:COUNT[0]'
        Info: Total cell delay = 1.351 ns ( 18.81 % )
        Info: Total interconnect delay = 5.831 ns ( 81.19 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 117 megabytes of memory during processing
    Info: Processing ended: Mon Nov 17 11:55:58 2008
    Info: Elapsed time: 00:00:01