📄 fivecall.map.rpt
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; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 46 ;
; -- arithmetic mode ; 25 ;
; ; ;
; Total registers ; 29 ;
; -- Dedicated logic registers ; 29 ;
; -- I/O registers ; 0 ;
; ; ;
; I/O pins ; 19 ;
; Maximum fan-out node ; DFRE:inst6|V_oNUM[2]~124 ;
; Maximum fan-out ; 29 ;
; Total fan-out ; 310 ;
; Average fan-out ; 2.61 ;
+---------------------------------------------+--------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
; |FIVECALL ; 71 (0) ; 29 (0) ; 0 ; 0 ; 0 ; 0 ; 19 ; 0 ; |FIVECALL ; work ;
; |COUNTER:inst| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIVECALL|COUNTER:inst ; work ;
; |DFRE:inst6| ; 38 (38) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIVECALL|DFRE:inst6 ; work ;
; |FTIMER:inst8| ; 24 (24) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIVECALL|FTIMER:inst8 ; work ;
; |KEY:inst3| ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |FIVECALL|KEY:inst3 ; work ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; FTIMER:inst8|S_oLED[6] ; FTIMER:inst8|Mux6 ; yes ;
; FTIMER:inst8|S_oLED[5] ; FTIMER:inst8|Mux6 ; yes ;
; FTIMER:inst8|S_oLED[4] ; FTIMER:inst8|Mux6 ; yes ;
; FTIMER:inst8|S_oLED[3] ; FTIMER:inst8|Mux6 ; yes ;
; FTIMER:inst8|S_oLED[2] ; FTIMER:inst8|Mux6 ; yes ;
; FTIMER:inst8|S_oLED[1] ; FTIMER:inst8|Mux6 ; yes ;
; FTIMER:inst8|S_oLED[0] ; FTIMER:inst8|Mux6 ; yes ;
; Number of user-specified and inferred latches = 7 ; ; ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops ;
+--------------------------------------------------------+---+
; Logic Cell Name ; ;
+--------------------------------------------------------+---+
; KEY:inst3|oKEY[4] ; ;
; KEY:inst3|oKEY[3] ; ;
; KEY:inst3|oKEY[2] ; ;
; KEY:inst3|oKEY[1] ; ;
; KEY:inst3|oKEY[0] ; ;
; Number of logic cells representing combinational loops ; 5 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 29 ;
; Number of registers using Synchronous Clear ; 26 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 3 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; 3:1 ; 26 bits ; 52 LEs ; 26 LEs ; 26 LEs ; Yes ; |FIVECALL|DFRE:inst6|fre[6] ;
; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |FIVECALL|DFRE:inst6|V_oNUM[2] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version
Info: Processing started: Tue Dec 02 18:43:48 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FIVECALL -c FIVECALL
Info: Found 2 design units, including 1 entities, in source file DFRE.vhd
Info: Found design unit 1: DFRE-run
Info: Found entity 1: DFRE
Info: Found 2 design units, including 1 entities, in source file COUNTER.vhd
Info: Found design unit 1: COUNTER-FUN
Info: Found entity 1: COUNTER
Info: Found 2 design units, including 1 entities, in source file FTIMER.vhd
Info: Found design unit 1: FTIMER-run
Info: Found entity 1: FTIMER
Info: Found 1 design units, including 1 entities, in source file FIVECALL.bdf
Info: Found entity 1: FIVECALL
Info: Found 2 design units, including 1 entities, in source file KEY.vhd
Info: Found design unit 1: KEY-FUN
Info: Found entity 1: KEY
Info: Elaborating entity "FIVECALL" for the top level hierarchy
Info: Elaborating entity "KEY" for hierarchy "KEY:inst3"
Warning (10492): VHDL Process Statement warning at KEY.vhd(19): signal "BKEY" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Elaborating entity "FTIMER" for hierarchy "FTIMER:inst8"
Warning (10492): VHDL Process Statement warning at FTIMER.vhd(24): signal "S_oLED" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at FTIMER.vhd(14): inferring latch(es) for signal or variable "S_oLED", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "S_oLED[0]" at FTIMER.vhd(14)
Info (10041): Inferred latch for "S_oLED[1]" at FTIMER.vhd(14)
Info (10041): Inferred latch for "S_oLED[2]" at FTIMER.vhd(14)
Info (10041): Inferred latch for "S_oLED[3]" at FTIMER.vhd(14)
Info (10041): Inferred latch for "S_oLED[4]" at FTIMER.vhd(14)
Info (10041): Inferred latch for "S_oLED[5]" at FTIMER.vhd(14)
Info (10041): Inferred latch for "S_oLED[6]" at FTIMER.vhd(14)
Info: Elaborating entity "COUNTER" for hierarchy "COUNTER:inst"
Warning: Using design file DFRE2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: DFRE2-run
Info: Found entity 1: DFRE2
Info: Elaborating entity "DFRE2" for hierarchy "DFRE2:inst2"
Info: Elaborating entity "DFRE" for hierarchy "DFRE:inst6"
Info: Duplicate LATCH primitives merged into single LATCH primitive
Info: Duplicate LATCH primitive "FTIMER:inst8|S_oLED[0]" merged with LATCH primitive "FTIMER:inst8|S_oLED[3]"
Warning: Latch FTIMER:inst8|S_oLED[6] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6|V_oNUM[2]
Warning: Latch FTIMER:inst8|S_oLED[5] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6|V_oNUM[2]
Warning: Latch FTIMER:inst8|S_oLED[4] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6|V_oNUM[2]
Warning: Latch FTIMER:inst8|S_oLED[3] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6|V_oNUM[2]
Warning: Latch FTIMER:inst8|S_oLED[2] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6|V_oNUM[2]
Warning: Latch FTIMER:inst8|S_oLED[1] has unsafe behavior
Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6|V_oNUM[2]
Info: Implemented 90 device resources after synthesis - the final resource count might be different
Info: Implemented 7 input pins
Info: Implemented 12 output pins
Info: Implemented 71 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings
Info: Allocated 162 megabytes of memory during processing
Info: Processing ended: Tue Dec 02 18:43:50 2008
Info: Elapsed time: 00:00:02
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