prev_cmp_fivecall.tan.qmsg

设计一个五路呼叫器,具体设计要求如下: 1．五个按键模拟五个呼叫源 2．当有一个按键按下时

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "DFRE:inst6\|V_oNUM\[1\] FTIMER:inst8\|S_oLED\[2\] iclk 2.044 ns " "Info: Found hold time violation between source  pin or register \"DFRE:inst6\|V_oNUM\[1\]\" and destination pin or register \"FTIMER:inst8\|S_oLED\[2\]\" for clock \"iclk\" (Hold time is 2.044 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.986 ns + Largest " "Info: + Largest clock skew is 3.986 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 7.481 ns + Longest register " "Info: + Longest clock path from clock \"iclk\" to destination register is 7.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 4; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.959 ns) + CELL(0.787 ns) 3.745 ns DFRE:inst6\|V_oNUM\[1\] 2 REG LCFF_X57_Y16_N23 15 " "Info: 2: + IC(1.959 ns) + CELL(0.787 ns) = 3.745 ns; Loc. = LCFF_X57_Y16_N23; Fanout = 15; REG Node = 'DFRE:inst6\|V_oNUM\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.746 ns" { iclk DFRE:inst6|V_oNUM[1] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.497 ns) + CELL(0.393 ns) 4.635 ns FTIMER:inst8\|Mux6~26 3 COMB LCCOMB_X58_Y16_N16 1 " "Info: 3: + IC(0.497 ns) + CELL(0.393 ns) = 4.635 ns; Loc. = LCCOMB_X58_Y16_N16; Fanout = 1; COMB Node = 'FTIMER:inst8\|Mux6~26'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.890 ns" { DFRE:inst6|V_oNUM[1] FTIMER:inst8|Mux6~26 } "NODE_NAME" } } { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.000 ns) 5.955 ns FTIMER:inst8\|Mux6~26clkctrl 4 COMB CLKCTRL_G6 6 " "Info: 4: + IC(1.320 ns) + CELL(0.000 ns) = 5.955 ns; Loc. = CLKCTRL_G6; Fanout = 6; COMB Node = 'FTIMER:inst8\|Mux6~26clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.320 ns" { FTIMER:inst8|Mux6~26 FTIMER:inst8|Mux6~26clkctrl } "NODE_NAME" } } { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.376 ns) + CELL(0.150 ns) 7.481 ns FTIMER:inst8\|S_oLED\[2\] 5 REG LCCOMB_X57_Y16_N6 1 " "Info: 5: + IC(1.376 ns) + CELL(0.150 ns) = 7.481 ns; Loc. = LCCOMB_X57_Y16_N6; Fanout = 1; REG Node = 'FTIMER:inst8\|S_oLED\[2\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.526 ns" { FTIMER:inst8|Mux6~26clkctrl FTIMER:inst8|S_oLED[2] } "NODE_NAME" } } { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.329 ns ( 31.13 % ) " "Info: Total cell delay = 2.329 ns ( 31.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.152 ns ( 68.87 % ) " "Info: Total interconnect delay = 5.152 ns ( 68.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.481 ns" { iclk DFRE:inst6|V_oNUM[1] FTIMER:inst8|Mux6~26 FTIMER:inst8|Mux6~26clkctrl FTIMER:inst8|S_oLED[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "7.481 ns" { iclk {} iclk~combout {} DFRE:inst6|V_oNUM[1] {} FTIMER:inst8|Mux6~26 {} FTIMER:inst8|Mux6~26clkctrl {} FTIMER:inst8|S_oLED[2] {} } { 0.000ns 0.000ns 1.959ns 0.497ns 1.320ns 1.376ns } { 0.000ns 0.999ns 0.787ns 0.393ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk source 3.495 ns - Shortest register " "Info: - Shortest clock path from clock \"iclk\" to source register is 3.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 4; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.959 ns) + CELL(0.537 ns) 3.495 ns DFRE:inst6\|V_oNUM\[1\] 2 REG LCFF_X57_Y16_N23 15 " "Info: 2: + IC(1.959 ns) + CELL(0.537 ns) = 3.495 ns; Loc. = LCFF_X57_Y16_N23; Fanout = 15; REG Node = 'DFRE:inst6\|V_oNUM\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { iclk DFRE:inst6|V_oNUM[1] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 43.95 % ) " "Info: Total cell delay = 1.536 ns ( 43.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.959 ns ( 56.05 % ) " "Info: Total interconnect delay = 1.959 ns ( 56.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.495 ns" { iclk DFRE:inst6|V_oNUM[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.495 ns" { iclk {} iclk~combout {} DFRE:inst6|V_oNUM[1] {} } { 0.000ns 0.000ns 1.959ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.481 ns" { iclk DFRE:inst6|V_oNUM[1] FTIMER:inst8|Mux6~26 FTIMER:inst8|Mux6~26clkctrl FTIMER:inst8|S_oLED[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "7.481 ns" { iclk {} iclk~combout {} DFRE:inst6|V_oNUM[1] {} FTIMER:inst8|Mux6~26 {} FTIMER:inst8|Mux6~26clkctrl {} FTIMER:inst8|S_oLED[2] {} } { 0.000ns 0.000ns 1.959ns 0.497ns 1.320ns 1.376ns } { 0.000ns 0.999ns 0.787ns 0.393ns 0.000ns 0.150ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.495 ns" { iclk DFRE:inst6|V_oNUM[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.495 ns" { iclk {} iclk~combout {} DFRE:inst6|V_oNUM[1] {} } { 0.000ns 0.000ns 1.959ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.692 ns - Shortest register register " "Info: - Shortest register to register delay is 1.692 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DFRE:inst6\|V_oNUM\[1\] 1 REG LCFF_X57_Y16_N23 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X57_Y16_N23; Fanout = 15; REG Node = 'DFRE:inst6\|V_oNUM\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DFRE:inst6|V_oNUM[1] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.342 ns) + CELL(0.150 ns) 0.492 ns FTIMER:inst8\|Mux1~398 2 COMB LCCOMB_X57_Y16_N20 2 " "Info: 2: + IC(0.342 ns) + CELL(0.150 ns) = 0.492 ns; Loc. = LCCOMB_X57_Y16_N20; Fanout = 2; COMB Node = 'FTIMER:inst8\|Mux1~398'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.492 ns" { DFRE:inst6|V_oNUM[1] FTIMER:inst8|Mux1~398 } "NODE_NAME" } } { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.245 ns) 1.004 ns FTIMER:inst8\|Mux1~400 3 COMB LCCOMB_X57_Y16_N28 1 " "Info: 3: + IC(0.267 ns) + CELL(0.245 ns) = 1.004 ns; Loc. = LCCOMB_X57_Y16_N28; Fanout = 1; COMB Node = 'FTIMER:inst8\|Mux1~400'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.512 ns" { FTIMER:inst8|Mux1~398 FTIMER:inst8|Mux1~400 } "NODE_NAME" } } { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.268 ns) + CELL(0.420 ns) 1.692 ns FTIMER:inst8\|S_oLED\[2\] 4 REG LCCOMB_X57_Y16_N6 1 " "Info: 4: + IC(0.268 ns) + CELL(0.420 ns) = 1.692 ns; Loc. = LCCOMB_X57_Y16_N6; Fanout = 1; REG Node = 'FTIMER:inst8\|S_oLED\[2\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.688 ns" { FTIMER:inst8|Mux1~400 FTIMER:inst8|S_oLED[2] } "NODE_NAME" } } { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.815 ns ( 48.17 % ) " "Info: Total cell delay = 0.815 ns ( 48.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.877 ns ( 51.83 % ) " "Info: Total interconnect delay = 0.877 ns ( 51.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.692 ns" { DFRE:inst6|V_oNUM[1] FTIMER:inst8|Mux1~398 FTIMER:inst8|Mux1~400 FTIMER:inst8|S_oLED[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "1.692 ns" { DFRE:inst6|V_oNUM[1] {} FTIMER:inst8|Mux1~398 {} FTIMER:inst8|Mux1~400 {} FTIMER:inst8|S_oLED[2] {} } { 0.000ns 0.342ns 0.267ns 0.268ns } { 0.000ns 0.150ns 0.245ns 0.420ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.481 ns" { iclk DFRE:inst6|V_oNUM[1] FTIMER:inst8|Mux6~26 FTIMER:inst8|Mux6~26clkctrl FTIMER:inst8|S_oLED[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "7.481 ns" { iclk {} iclk~combout {} DFRE:inst6|V_oNUM[1] {} FTIMER:inst8|Mux6~26 {} FTIMER:inst8|Mux6~26clkctrl {} FTIMER:inst8|S_oLED[2] {} } { 0.000ns 0.000ns 1.959ns 0.497ns 1.320ns 1.376ns } { 0.000ns 0.999ns 0.787ns 0.393ns 0.000ns 0.150ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.495 ns" { iclk DFRE:inst6|V_oNUM[1] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.495 ns" { iclk {} iclk~combout {} DFRE:inst6|V_oNUM[1] {} } { 0.000ns 0.000ns 1.959ns } { 0.000ns 0.999ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.692 ns" { DFRE:inst6|V_oNUM[1] FTIMER:inst8|Mux1~398 FTIMER:inst8|Mux1~400 FTIMER:inst8|S_oLED[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "1.692 ns" { DFRE:inst6|V_oNUM[1] {} FTIMER:inst8|Mux1~398 {} FTIMER:inst8|Mux1~400 {} FTIMER:inst8|S_oLED[2] {} } { 0.000ns 0.342ns 0.267ns 0.268ns } { 0.000ns 0.150ns 0.245ns 0.420ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "DFRE:inst6\|fre\[0\] iRES iclk 5.443 ns register " "Info: tsu for register \"DFRE:inst6\|fre\[0\]\" (data pin = \"iRES\", clock pin = \"iclk\") is 5.443 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.162 ns + Longest pin register " "Info: + Longest pin to register delay is 8.162 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns iRES 1 PIN PIN_W26 9 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_W26; Fanout = 9; PIN Node = 'iRES'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iRES } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -8 -240 -72 8 "iRES" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.646 ns) + CELL(0.438 ns) 6.946 ns DFRE:inst6\|V_oNUM\[2\]~124 2 COMB LCCOMB_X56_Y15_N28 29 " "Info: 2: + IC(5.646 ns) + CELL(0.438 ns) = 6.946 ns; Loc. = LCCOMB_X56_Y15_N28; Fanout = 29; COMB Node = 'DFRE:inst6\|V_oNUM\[2\]~124'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.084 ns" { iRES DFRE:inst6|V_oNUM[2]~124 } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.510 ns) 8.162 ns DFRE:inst6\|fre\[0\] 3 REG LCFF_X56_Y16_N7 3 " "Info: 3: + IC(0.706 ns) + CELL(0.510 ns) = 8.162 ns; Loc. = LCFF_X56_Y16_N7; Fanout = 3; REG Node = 'DFRE:inst6\|fre\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.216 ns" { DFRE:inst6|V_oNUM[2]~124 DFRE:inst6|fre[0] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.810 ns ( 22.18 % ) " "Info: Total cell delay = 1.810 ns ( 22.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.352 ns ( 77.82 % ) " "Info: Total interconnect delay = 6.352 ns ( 77.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.162 ns" { iRES DFRE:inst6|V_oNUM[2]~124 DFRE:inst6|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "8.162 ns" { iRES {} iRES~combout {} DFRE:inst6|V_oNUM[2]~124 {} DFRE:inst6|fre[0] {} } { 0.000ns 0.000ns 5.646ns 0.706ns } { 0.000ns 0.862ns 0.438ns 0.510ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 2.683 ns - Shortest register " "Info: - Shortest clock path from clock \"iclk\" to destination register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 4; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'iclk~clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.537 ns) 2.683 ns DFRE:inst6\|fre\[0\] 3 REG LCFF_X56_Y16_N7 3 " "Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X56_Y16_N7; Fanout = 3; REG Node = 'DFRE:inst6\|fre\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { iclk~clkctrl DFRE:inst6|fre[0] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.25 % ) " "Info: Total cell delay = 1.536 ns ( 57.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.147 ns ( 42.75 % ) " "Info: Total interconnect delay = 1.147 ns ( 42.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { iclk iclk~clkctrl DFRE:inst6|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DFRE:inst6|fre[0] {} } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.162 ns" { iRES DFRE:inst6|V_oNUM[2]~124 DFRE:inst6|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "8.162 ns" { iRES {} iRES~combout {} DFRE:inst6|V_oNUM[2]~124 {} DFRE:inst6|fre[0] {} } { 0.000ns 0.000ns 5.646ns 0.706ns } { 0.000ns 0.862ns 0.438ns 0.510ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { iclk iclk~clkctrl DFRE:inst6|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DFRE:inst6|fre[0] {} } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "iclk oLED\[0\] FTIMER:inst8\|S_oLED\[3\] 14.105 ns register " "Info: tco from clock \"iclk\" to destination pin \"oLED\[0\]\" through register \"FTIMER:inst8\|S_oLED\[3\]\" is 14.105 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk source 7.454 ns + Longest register " "Info: + Longest clock path from clock \"iclk\" to source register is 7.454 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 4; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.959 ns) + CELL(0.787 ns) 3.745 ns DFRE:inst6\|V_oNUM\[1\] 2 REG LCFF_X57_Y16_N23 15 " "Info: 2: + IC(1.959 ns) + CELL(0.787 ns) = 3.745 ns; Loc. = LCFF_X57_Y16_N23; Fanout = 15; REG Node = 'DFRE:inst6\|V_oNUM\[1\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.746 ns" { iclk DFRE:inst6|V_oNUM[1] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.497 ns) + CELL(0.393 ns) 4.635 ns FTIMER:inst8\|Mux6~26 3 COMB LCCOMB_X58_Y16_N16 1 " "Info: 3: + IC(0.497 ns) + CELL(0.393 ns) = 4.635 ns; Loc. = LCCOMB_X58_Y16_N16; Fanout = 1; COMB Node = 'FTIMER:inst8\|Mux6~26'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.890 ns" { DFRE:inst6|V_oNUM[1] FTIMER:inst8|Mux6~26 } "NODE_NAME" } } { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.320 ns) + CELL(0.000 ns) 5.955 ns FTIMER:inst8\|Mux6~26clkctrl 4 COMB CLKCTRL_G6 6 " "Info: 4: + IC(1.320 ns) + CELL(0.000 ns) = 5.955 ns; Loc. = CLKCTRL_G6; Fanout = 6; COMB Node = 'FTIMER:inst8\|Mux6~26clkctrl'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.320 ns" { FTIMER:inst8|Mux6~26 FTIMER:inst8|Mux6~26clkctrl } "NODE_NAME" } } { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.150 ns) 7.454 ns FTIMER:inst8\|S_oLED\[3\] 5 REG LCCOMB_X59_Y16_N8 2 " "Info: 5: + IC(1.349 ns) + CELL(0.150 ns) = 7.454 ns; Loc. = LCCOMB_X59_Y16_N8; Fanout = 2; REG Node = 'FTIMER:inst8\|S_oLED\[3\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { FTIMER:inst8|Mux6~26clkctrl FTIMER:inst8|S_oLED[3] } "NODE_NAME" } } { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.329 ns ( 31.24 % ) " "Info: Total cell delay = 2.329 ns ( 31.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.125 ns ( 68.76 % ) " "Info: Total interconnect delay = 5.125 ns ( 68.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.454 ns" { iclk DFRE:inst6|V_oNUM[1] FTIMER:inst8|Mux6~26 FTIMER:inst8|Mux6~26clkctrl FTIMER:inst8|S_oLED[3] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "7.454 ns" { iclk {} iclk~combout {} DFRE:inst6|V_oNUM[1] {} FTIMER:inst8|Mux6~26 {} FTIMER:inst8|Mux6~26clkctrl {} FTIMER:inst8|S_oLED[3] {} } { 0.000ns 0.000ns 1.959ns 0.497ns 1.320ns 1.349ns } { 0.000ns 0.999ns 0.787ns 0.393ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.651 ns + Longest register pin " "Info: + Longest register to pin delay is 6.651 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FTIMER:inst8\|S_oLED\[3\] 1 REG LCCOMB_X59_Y16_N8 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X59_Y16_N8; Fanout = 2; REG Node = 'FTIMER:inst8\|S_oLED\[3\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FTIMER:inst8|S_oLED[3] } "NODE_NAME" } } { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.853 ns) + CELL(2.798 ns) 6.651 ns oLED\[0\] 2 PIN PIN_AF10 0 " "Info: 2: + IC(3.853 ns) + CELL(2.798 ns) = 6.651 ns; Loc. = PIN_AF10; Fanout = 0; PIN Node = 'oLED\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.651 ns" { FTIMER:inst8|S_oLED[3] oLED[0] } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { 8 688 864 24 "oLED\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 42.07 % ) " "Info: Total cell delay = 2.798 ns ( 42.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.853 ns ( 57.93 % ) " "Info: Total interconnect delay = 3.853 ns ( 57.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.651 ns" { FTIMER:inst8|S_oLED[3] oLED[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "6.651 ns" { FTIMER:inst8|S_oLED[3] {} oLED[0] {} } { 0.000ns 3.853ns } { 0.000ns 2.798ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.454 ns" { iclk DFRE:inst6|V_oNUM[1] FTIMER:inst8|Mux6~26 FTIMER:inst8|Mux6~26clkctrl FTIMER:inst8|S_oLED[3] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "7.454 ns" { iclk {} iclk~combout {} DFRE:inst6|V_oNUM[1] {} FTIMER:inst8|Mux6~26 {} FTIMER:inst8|Mux6~26clkctrl {} FTIMER:inst8|S_oLED[3] {} } { 0.000ns 0.000ns 1.959ns 0.497ns 1.320ns 1.349ns } { 0.000ns 0.999ns 0.787ns 0.393ns 0.000ns 0.150ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.651 ns" { FTIMER:inst8|S_oLED[3] oLED[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "6.651 ns" { FTIMER:inst8|S_oLED[3] {} oLED[0] {} } { 0.000ns 3.853ns } { 0.000ns 2.798ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "DFRE:inst6\|V_oNUM\[0\] iRES iclk -3.120 ns register " "Info: th for register \"DFRE:inst6\|V_oNUM\[0\]\" (data pin = \"iRES\", clock pin = \"iclk\") is -3.120 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 3.495 ns + Longest register " "Info: + Longest clock path from clock \"iclk\" to destination register is 3.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 4; CLK Node = 'iclk'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.959 ns) + CELL(0.537 ns) 3.495 ns DFRE:inst6\|V_oNUM\[0\] 2 REG LCFF_X57_Y16_N31 16 " "Info: 2: + IC(1.959 ns) + CELL(0.537 ns) = 3.495 ns; Loc. = LCFF_X57_Y16_N31; Fanout = 16; REG Node = 'DFRE:inst6\|V_oNUM\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { iclk DFRE:inst6|V_oNUM[0] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 43.95 % ) " "Info: Total cell delay = 1.536 ns ( 43.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.959 ns ( 56.05 % ) " "Info: Total interconnect delay = 1.959 ns ( 56.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.495 ns" { iclk DFRE:inst6|V_oNUM[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.495 ns" { iclk {} iclk~combout {} DFRE:inst6|V_oNUM[0] {} } { 0.000ns 0.000ns 1.959ns } { 0.000ns 0.999ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.881 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.881 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.862 ns) 0.862 ns iRES 1 PIN PIN_W26 9 " "Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_W26; Fanout = 9; PIN Node = 'iRES'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iRES } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -8 -240 -72 8 "iRES" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.497 ns) + CELL(0.438 ns) 6.797 ns DFRE:inst6\|V_oNUM~123 2 COMB LCCOMB_X57_Y16_N30 1 " "Info: 2: + IC(5.497 ns) + CELL(0.438 ns) = 6.797 ns; Loc. = LCCOMB_X57_Y16_N30; Fanout = 1; COMB Node = 'DFRE:inst6\|V_oNUM~123'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.935 ns" { iRES DFRE:inst6|V_oNUM~123 } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 6.881 ns DFRE:inst6\|V_oNUM\[0\] 3 REG LCFF_X57_Y16_N31 16 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.881 ns; Loc. = LCFF_X57_Y16_N31; Fanout = 16; REG Node = 'DFRE:inst6\|V_oNUM\[0\]'" {  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { DFRE:inst6|V_oNUM~123 DFRE:inst6|V_oNUM[0] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.384 ns ( 20.11 % ) " "Info: Total cell delay = 1.384 ns ( 20.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.497 ns ( 79.89 % ) " "Info: Total interconnect delay = 5.497 ns ( 79.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.881 ns" { iRES DFRE:inst6|V_oNUM~123 DFRE:inst6|V_oNUM[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "6.881 ns" { iRES {} iRES~combout {} DFRE:inst6|V_oNUM~123 {} DFRE:inst6|V_oNUM[0] {} } { 0.000ns 0.000ns 5.497ns 0.000ns } { 0.000ns 0.862ns 0.438ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.495 ns" { iclk DFRE:inst6|V_oNUM[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.495 ns" { iclk {} iclk~combout {} DFRE:inst6|V_oNUM[0] {} } { 0.000ns 0.000ns 1.959ns } { 0.000ns 0.999ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.881 ns" { iRES DFRE:inst6|V_oNUM~123 DFRE:inst6|V_oNUM[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "6.881 ns" { iRES {} iRES~combout {} DFRE:inst6|V_oNUM~123 {} DFRE:inst6|V_oNUM[0] {} } { 0.000ns 0.000ns 5.497ns 0.000ns } { 0.000ns 0.862ns 0.438ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}