📄 prev_cmp_fivecall.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 02 18:32:03 2008 " "Info: Processing started: Tue Dec 02 18:32:03 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off FIVECALL -c FIVECALL " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off FIVECALL -c FIVECALL" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "195 " "Info: Allocated 195 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 02 18:32:14 2008 " "Info: Processing ended: Tue Dec 02 18:32:14 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 02 18:32:15 2008 " "Info: Processing started: Tue Dec 02 18:32:15 2008" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off FIVECALL -c FIVECALL --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FIVECALL -c FIVECALL --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "KEY:inst3\|BKEY~25 " "Warning: Node \"KEY:inst3\|BKEY~25\" is a latch" { } { { "KEY.vhd" "" { Text "D:/fivecall/KEY.vhd" 13 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "KEY:inst3\|BKEY~26 " "Warning: Node \"KEY:inst3\|BKEY~26\" is a latch" { } { { "KEY.vhd" "" { Text "D:/fivecall/KEY.vhd" 13 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "KEY:inst3\|BKEY~27 " "Warning: Node \"KEY:inst3\|BKEY~27\" is a latch" { } { { "KEY.vhd" "" { Text "D:/fivecall/KEY.vhd" 13 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "KEY:inst3\|BKEY~28 " "Warning: Node \"KEY:inst3\|BKEY~28\" is a latch" { } { { "KEY.vhd" "" { Text "D:/fivecall/KEY.vhd" 13 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "KEY:inst3\|BKEY~29 " "Warning: Node \"KEY:inst3\|BKEY~29\" is a latch" { } { { "KEY.vhd" "" { Text "D:/fivecall/KEY.vhd" 13 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "FTIMER:inst8\|S_oLED\[6\] " "Warning: Node \"FTIMER:inst8\|S_oLED\[6\]\" is a latch" { } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "FTIMER:inst8\|S_oLED\[5\] " "Warning: Node \"FTIMER:inst8\|S_oLED\[5\]\" is a latch" { } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "FTIMER:inst8\|S_oLED\[4\] " "Warning: Node \"FTIMER:inst8\|S_oLED\[4\]\" is a latch" { } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "FTIMER:inst8\|S_oLED\[3\] " "Warning: Node \"FTIMER:inst8\|S_oLED\[3\]\" is a latch" { } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "FTIMER:inst8\|S_oLED\[2\] " "Warning: Node \"FTIMER:inst8\|S_oLED\[2\]\" is a latch" { } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "FTIMER:inst8\|S_oLED\[1\] " "Warning: Node \"FTIMER:inst8\|S_oLED\[1\]\" is a latch" { } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} } { } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "iclk " "Info: Assuming node \"iclk\" is an undefined clock" { } { { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "iclk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "FTIMER:inst8\|Mux6~26 " "Info: Detected gated clock \"FTIMER:inst8\|Mux6~26\" as buffer" { } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 16 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FTIMER:inst8\|Mux6~26" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DFRE:inst6\|V_oNUM\[1\] " "Info: Detected ripple clock \"DFRE:inst6\|V_oNUM\[1\]\" as buffer" { } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DFRE:inst6\|V_oNUM\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DFRE:inst6\|V_oNUM\[2\] " "Info: Detected ripple clock \"DFRE:inst6\|V_oNUM\[2\]\" as buffer" { } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DFRE:inst6\|V_oNUM\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "DFRE:inst6\|V_oNUM\[0\] " "Info: Detected ripple clock \"DFRE:inst6\|V_oNUM\[0\]\" as buffer" { } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } } { "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/quartus72lite/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DFRE:inst6\|V_oNUM\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "iclk register DFRE:inst6\|fre\[2\] register DFRE:inst6\|fre\[0\] 250.0 MHz 4.0 ns Internal " "Info: Clock \"iclk\" has Internal fmax of 250.0 MHz between source register \"DFRE:inst6\|fre\[2\]\" and destination register \"DFRE:inst6\|fre\[0\]\" (period= 4.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.786 ns + Longest register register " "Info: + Longest register to register delay is 3.786 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DFRE:inst6\|fre\[2\] 1 REG LCFF_X56_Y16_N11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X56_Y16_N11; Fanout = 3; REG Node = 'DFRE:inst6\|fre\[2\]'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DFRE:inst6|fre[2] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.338 ns) + CELL(0.438 ns) 0.776 ns DFRE:inst6\|Equal0~262 2 COMB LCCOMB_X56_Y16_N2 1 " "Info: 2: + IC(0.338 ns) + CELL(0.438 ns) = 0.776 ns; Loc. = LCCOMB_X56_Y16_N2; Fanout = 1; COMB Node = 'DFRE:inst6\|Equal0~262'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.776 ns" { DFRE:inst6|fre[2] DFRE:inst6|Equal0~262 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.959 ns) + CELL(0.438 ns) 2.173 ns DFRE:inst6\|Equal0~266 3 COMB LCCOMB_X56_Y15_N30 1 " "Info: 3: + IC(0.959 ns) + CELL(0.438 ns) = 2.173 ns; Loc. = LCCOMB_X56_Y15_N30; Fanout = 1; COMB Node = 'DFRE:inst6\|Equal0~266'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.397 ns" { DFRE:inst6|Equal0~262 DFRE:inst6|Equal0~266 } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/quartus72lite/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 2.570 ns DFRE:inst6\|V_oNUM\[2\]~124 4 COMB LCCOMB_X56_Y15_N28 29 " "Info: 4: + IC(0.247 ns) + CELL(0.150 ns) = 2.570 ns; Loc. = LCCOMB_X56_Y15_N28; Fanout = 29; COMB Node = 'DFRE:inst6\|V_oNUM\[2\]~124'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.397 ns" { DFRE:inst6|Equal0~266 DFRE:inst6|V_oNUM[2]~124 } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.706 ns) + CELL(0.510 ns) 3.786 ns DFRE:inst6\|fre\[0\] 5 REG LCFF_X56_Y16_N7 3 " "Info: 5: + IC(0.706 ns) + CELL(0.510 ns) = 3.786 ns; Loc. = LCFF_X56_Y16_N7; Fanout = 3; REG Node = 'DFRE:inst6\|fre\[0\]'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.216 ns" { DFRE:inst6|V_oNUM[2]~124 DFRE:inst6|fre[0] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 40.57 % ) " "Info: Total cell delay = 1.536 ns ( 40.57 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.250 ns ( 59.43 % ) " "Info: Total interconnect delay = 2.250 ns ( 59.43 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.786 ns" { DFRE:inst6|fre[2] DFRE:inst6|Equal0~262 DFRE:inst6|Equal0~266 DFRE:inst6|V_oNUM[2]~124 DFRE:inst6|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.786 ns" { DFRE:inst6|fre[2] {} DFRE:inst6|Equal0~262 {} DFRE:inst6|Equal0~266 {} DFRE:inst6|V_oNUM[2]~124 {} DFRE:inst6|fre[0] {} } { 0.000ns 0.338ns 0.959ns 0.247ns 0.706ns } { 0.000ns 0.438ns 0.438ns 0.150ns 0.510ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 2.683 ns + Shortest register " "Info: + Shortest clock path from clock \"iclk\" to destination register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 4; CLK Node = 'iclk'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'iclk~clkctrl'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.537 ns) 2.683 ns DFRE:inst6\|fre\[0\] 3 REG LCFF_X56_Y16_N7 3 " "Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X56_Y16_N7; Fanout = 3; REG Node = 'DFRE:inst6\|fre\[0\]'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { iclk~clkctrl DFRE:inst6|fre[0] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.25 % ) " "Info: Total cell delay = 1.536 ns ( 57.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.147 ns ( 42.75 % ) " "Info: Total interconnect delay = 1.147 ns ( 42.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { iclk iclk~clkctrl DFRE:inst6|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DFRE:inst6|fre[0] {} } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk source 2.683 ns - Longest register " "Info: - Longest clock path from clock \"iclk\" to source register is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 4; CLK Node = 'iclk'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns iclk~clkctrl 2 COMB CLKCTRL_G2 26 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 26; COMB Node = 'iclk~clkctrl'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { iclk iclk~clkctrl } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.029 ns) + CELL(0.537 ns) 2.683 ns DFRE:inst6\|fre\[2\] 3 REG LCFF_X56_Y16_N11 3 " "Info: 3: + IC(1.029 ns) + CELL(0.537 ns) = 2.683 ns; Loc. = LCFF_X56_Y16_N11; Fanout = 3; REG Node = 'DFRE:inst6\|fre\[2\]'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.566 ns" { iclk~clkctrl DFRE:inst6|fre[2] } "NODE_NAME" } } { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.25 % ) " "Info: Total cell delay = 1.536 ns ( 57.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.147 ns ( 42.75 % ) " "Info: Total interconnect delay = 1.147 ns ( 42.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { iclk iclk~clkctrl DFRE:inst6|fre[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DFRE:inst6|fre[2] {} } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { iclk iclk~clkctrl DFRE:inst6|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DFRE:inst6|fre[0] {} } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { iclk iclk~clkctrl DFRE:inst6|fre[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DFRE:inst6|fre[2] {} } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.786 ns" { DFRE:inst6|fre[2] DFRE:inst6|Equal0~262 DFRE:inst6|Equal0~266 DFRE:inst6|V_oNUM[2]~124 DFRE:inst6|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "3.786 ns" { DFRE:inst6|fre[2] {} DFRE:inst6|Equal0~262 {} DFRE:inst6|Equal0~266 {} DFRE:inst6|V_oNUM[2]~124 {} DFRE:inst6|fre[0] {} } { 0.000ns 0.338ns 0.959ns 0.247ns 0.706ns } { 0.000ns 0.438ns 0.438ns 0.150ns 0.510ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { iclk iclk~clkctrl DFRE:inst6|fre[0] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DFRE:inst6|fre[0] {} } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.683 ns" { iclk iclk~clkctrl DFRE:inst6|fre[2] } "NODE_NAME" } } { "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/quartus72lite/altera/72/quartus/bin/Technology_Viewer.qrui" "2.683 ns" { iclk {} iclk~combout {} iclk~clkctrl {} DFRE:inst6|fre[2] {} } { 0.000ns 0.000ns 0.118ns 1.029ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "iclk 18 " "Warning: Circuit may not operate. Detected 18 non-operational path(s) clocked by clock \"iclk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "DFRE:inst6\|V_oNUM\[1\] FTIMER:inst8\|S_oLED\[2\] iclk 2.044 ns " "Info: Found hold time violation between source pin or register \"DFRE:inst6\|V_oNUM\[1\]\" and destination pin or register \"FTIMER:inst8\|S_oLED\[2\]\" for clock \"iclk\" (Hold time is 2.044 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "3.986 ns + Largest " "Info: + Largest clock skew is 3.986 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "iclk destination 7.481 ns + Longest register " "Info: + Longest clock path from clock \"iclk\" to destination register is 7.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns iclk 1 CLK PIN_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 4; CLK Node = 'iclk'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { iclk } "NODE_NAME" } } { "FIVECALL.bdf" "" { Schematic "D:/fivecall/FIVECALL.bdf" { { -24 -240 -72 -8 "iclk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.959 ns) + CELL(0.787 ns) 3.745 ns DFRE:inst6\|V_oNUM\[1\] 2 REG LCFF_X57_Y16_N23 15 " "Info: 2: + IC(1.959 ns) + CELL(0.787 ns) = 3.745 ns; Loc. = LCFF_X57_Y16_N23; Fanout = 15; REG Node = 'DFRE:inst6\|V_oNUM\[1\]'" { } { { "c:/quartus72lite/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/quartus72lite/altera/72/quartus/bin/T⌨️ 快捷键说明
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