prev_cmp_fivecall.qmsg

设计一个五路呼叫器,具体设计要求如下: 1．五个按键模拟五个呼叫源 2．当有一个按键按下时

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "S_oLED\[4\] FTIMER.vhd(14) " "Info (10041): Inferred latch for \"S_oLED\[4\]\" at FTIMER.vhd(14)" {  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "S_oLED\[5\] FTIMER.vhd(14) " "Info (10041): Inferred latch for \"S_oLED\[5\]\" at FTIMER.vhd(14)" {  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "S_oLED\[6\] FTIMER.vhd(14) " "Info (10041): Inferred latch for \"S_oLED\[6\]\" at FTIMER.vhd(14)" {  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "COUNTER COUNTER:inst " "Info: Elaborating entity \"COUNTER\" for hierarchy \"COUNTER:inst\"" {  } { { "FIVECALL.bdf" "inst" { Schematic "D:/fivecall/FIVECALL.bdf" { { -64 248 400 32 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "DFRE2.vhd 2 1 " "Warning: Using design file DFRE2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DFRE2-run " "Info: Found design unit 1: DFRE2-run" {  } { { "DFRE2.vhd" "" { Text "D:/fivecall/DFRE2.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 DFRE2 " "Info: Found entity 1: DFRE2" {  } { { "DFRE2.vhd" "" { Text "D:/fivecall/DFRE2.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DFRE2 DFRE2:inst2 " "Info: Elaborating entity \"DFRE2\" for hierarchy \"DFRE2:inst2\"" {  } { { "FIVECALL.bdf" "inst2" { Schematic "D:/fivecall/FIVECALL.bdf" { { -176 80 176 -80 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DFRE DFRE:inst6 " "Info: Elaborating entity \"DFRE\" for hierarchy \"DFRE:inst6\"" {  } { { "FIVECALL.bdf" "inst6" { Schematic "D:/fivecall/FIVECALL.bdf" { { -48 64 200 48 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_LATCH_INFO_HDR" "" "Info: Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IOPT_MLS_DUP_LATCH_INFO" "FTIMER:inst8\|S_oLED\[0\] FTIMER:inst8\|S_oLED\[3\] " "Info: Duplicate LATCH primitive \"FTIMER:inst8\|S_oLED\[0\]\" merged with LATCH primitive \"FTIMER:inst8\|S_oLED\[3\]\"" {  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate LATCH primitives merged into single LATCH primitive" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "FTIMER:inst8\|S_oLED\[6\] " "Warning: Latch FTIMER:inst8\|S_oLED\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA DFRE:inst6\|V_oNUM\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6\|V_oNUM\[2\]" {  } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "FTIMER:inst8\|S_oLED\[5\] " "Warning: Latch FTIMER:inst8\|S_oLED\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA DFRE:inst6\|V_oNUM\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6\|V_oNUM\[2\]" {  } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "FTIMER:inst8\|S_oLED\[4\] " "Warning: Latch FTIMER:inst8\|S_oLED\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA DFRE:inst6\|V_oNUM\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6\|V_oNUM\[2\]" {  } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "FTIMER:inst8\|S_oLED\[3\] " "Warning: Latch FTIMER:inst8\|S_oLED\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA DFRE:inst6\|V_oNUM\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6\|V_oNUM\[2\]" {  } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "FTIMER:inst8\|S_oLED\[2\] " "Warning: Latch FTIMER:inst8\|S_oLED\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA DFRE:inst6\|V_oNUM\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6\|V_oNUM\[2\]" {  } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "FTIMER:inst8\|S_oLED\[1\] " "Warning: Latch FTIMER:inst8\|S_oLED\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA DFRE:inst6\|V_oNUM\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal DFRE:inst6\|V_oNUM\[2\]" {  } { { "DFRE.vhd" "" { Text "D:/fivecall/DFRE.vhd" 18 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "FTIMER.vhd" "" { Text "D:/fivecall/FTIMER.vhd" 14 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "90 " "Info: Implemented 90 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "12 " "Info: Implemented 12 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "71 " "Info: Implemented 71 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 16 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "162 " "Info: Allocated 162 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 02 18:31:50 2008 " "Info: Processing ended: Tue Dec 02 18:31:50 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version " "Info: Version 7.2 Build 175 11/20/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 02 18:31:51 2008 " "Info: Processing started: Tue Dec 02 18:31:51 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}