asyn_fifo.v

verilog编写的异步fifo源代码

`timescale 1ns/10ps
`default_nettype none

module asyn_fifo
#(
	parameter
	DATA_WIDTH = 16,
	ADDR_WIDTH = 4
)
(
	input wire rst_n,

	input wire input_clk,
	input wire [15:0] input_data,

	input wire output_clk,
	output wire [15:0] output_data
);

wire [ADDR_WIDTH-1:0] w_ptr;
wire [ADDR_WIDTH-1:0] r_ptr;
wire asyn_empty;
wire asyn_full;

dp_ram
#(
	.DATA_WIDTH(DATA_WIDTH),
	.ADDR_WIDTH(ADDR_WIDTH),
	.DEPTH(2**ADDR_WIDTH)
)
U1_dp_ram
(
	.rdata(output_data),
	.wdata(input_data),
	.waddr(w_ptr),
	.raddr(r_ptr),
	.w_clk(input_clk)
);

asyn_comp
#(
	.ADDR_WIDTH(ADDR_WIDTH)
)
U2_asyn_comp
(
	.asyn_empty(asyn_empty),
	.asyn_full(asyn_full),
	.rst_n(rst_n),
	.w_ptr(w_ptr),
	.r_ptr(r_ptr)
);

write_ptr
#(
	.ADDR_WIDTH(ADDR_WIDTH)
)
U3_write_ptr
(
	.w_ptr(w_ptr),
	.rst_n(rst_n),
	.w_clk(input_clk),
	.w_req(1'b1),
	
	//读空标志
	.asyn_full(asyn_full),
	.w_full()
);

read_ptr
#(
	.ADDR_WIDTH(ADDR_WIDTH)
)
U4_read_ptr
(
	.r_ptr(r_ptr),
	.rst_n(rst_n),
	.r_clk(output_clk),
	.r_req(1'b1),
	
	//读空标志
	.asyn_empty(asyn_empty),
	.r_empty()
);

endmodule