read_ptr.v

来自「verilog编写的异步fifo源代码」· Verilog 代码 · 共 54 行

//读指针逻辑模块
module read_ptr
#(
	parameter
	ADDR_WIDTH = 4
)
(
	output reg [ADDR_WIDTH-1 : 0] r_ptr,
	input wire rst_n,
	input wire r_clk,
	input wire r_req,
	
	//读空标志
	input wire asyn_empty,
	output reg r_empty
);

reg [ADDR_WIDTH-1 : 0] rbin;
wire [ADDR_WIDTH-1 : 0] rgnext, rbnext;

//寄存输出gray码读地址指针
always @ (posedge r_clk or negedge rst_n)
	if(rst_n == 1'b0)
	begin
		r_ptr <= 0;
		rbin <= 0;
	end
	else
	begin
		r_ptr <= rgnext;
		rbin <= rbnext;
	end

//输出读空标志
reg r_empty1;

always @ (posedge r_clk or negedge asyn_empty)
	if(asyn_empty == 1'b0)
	begin
		r_empty <= 1'b1;
		r_empty1 <= 1'b1;
	end
	else
	begin
		r_empty1 <= ~asyn_empty;
		r_empty <= r_empty1;
	end

//读地址计数
assign rbnext = (r_empty == 1'b0) ? (rbin + r_req) : rbin;
//二进制到gray码转换
assign rgnext = (rbnext>>1) ^ rbnext;

endmodule