write_ptr.v

verilog编写的异步fifo源代码

//写指针逻辑模块
module write_ptr
#(
	parameter
	ADDR_WIDTH = 4
)
(
	output reg [ADDR_WIDTH-1 : 0] w_ptr,
	input wire rst_n,
	input wire w_clk,
	input wire w_req,
	
	//读空标志
	input wire asyn_full,
	output reg w_full
);

reg [ADDR_WIDTH-1 : 0] wbin;
wire [ADDR_WIDTH-1 : 0] wgnext, wbnext;

//寄存输出gray码写地址指针

always @ (posedge w_clk or negedge rst_n)
	if(rst_n == 1'b0)
	begin
		w_ptr <= 0;
		wbin <= 0;
	end
	else
	begin
		w_ptr <= wgnext;
		wbin <= wbnext;
	end

//输出写满标志

reg w_full1;

always @ (posedge w_clk or negedge asyn_full or negedge rst_n)
	if(rst_n == 1'b0)
	begin
		w_full <= 1'b0;
		w_full1 <= 1'b0;
	end
	else if(asyn_full == 1'b0)
	begin
		w_full <= 1'b1;
		w_full1 <= 1'b1;
	end
	else
	begin
		w_full1 <= ~asyn_full;
		w_full <= w_full1;
	end

//写地址计数
assign wbnext = (w_full == 1'b0) ? (wbin + w_req) : wbin;
//二进制到gray码转换
assign wgnext = (wbnext >> 1) ^ wbnext;

endmodule