9人表决器.txt

移位寄存器和9人表决器电路的VHDL设计方案

module biaojueqi(vote,ledr,ledg,dis_out); 
input [8:0] vote; 
output ledr,ledg; 
output [6:0] dis_out; 
reg [6:0] dis_out; 
integer i,sum; //sum表示赞同的人数 
always @(vote) 
begin 
sum<=0; 
for(i=0;i<=8;i=i+1) 
if(vote[i]) sum<=sum+1; 
if(sum>4) begin ledg<=1;ledr<=0;end 
else begin ledg<=0;ledr<=1;end 
end 
always @(sum) //结果由dis_out显示在数码管上 
begin 
case (sum) 
0: dis_out[6:0]<=7'b1111110; 
1: dis_out[6:0]<=7'b0110000; 
2: dis_out[6:0]<=7'b1101101; 
3: dis_out[6:0]<=7'b1111001; 
4: dis_out[6:0]<=7'b0110011; 
5: dis_out[6:0]<=7'b1011011; 
6: dis_out[6:0]<=7'b1011111; 
7: dis_out[6:0]<=7'b1110000; 
8: dis_out[6:0]<=7'b1111111; 
9: dis_out[6:0]<=7'b1111011; 
default:dis_out[6:0]<=7'bx; 
endcase 
end 
endmodule