cnt6.vhd.bak

来自「利用数控分频器设计硬件电子琴.硬件电子琴电路模块设计」· BAK 代码 · 共 28 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CNT6 IS
  PORT(clk2:IN STD_LOGIC;
       Q2: OUT STD_LOGIC);
END CNT6;

ARCHITECTURE ddy OF CNT6 IS
SIGNAL s:STD_LOGIC;
SIGNAL mi:INTEGER RANGE 1 TO 3375000;
BEGIN
PROCESS(clk2)
BEGIN
    IF (clk2'EVENT AND clk2='1') THEN
        IF(MI=3375000) THEN
			MI<=1;
			S<=NOT S;
			ELSIF(MI<3375000) THEN
			    MI<=MI+1;
				ELSIF(MI=1687500) THEN
					S<=NOT S;		
		END IF;
	Q2<=S;
    END IF;
END PROCESS;
END ddy;