cnt4.vhd.bak

利用数控分频器设计硬件电子琴.硬件电子琴电路模块设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CNT4 IS
  PORT(clk4:IN STD_LOGIC;
       Q4: OUT STD_LOGIC);
END CNT4;

ARCHITECTURE behav OF CNT4 IS
SIGNAL q:STD_LOGIC;
SIGNAL ni:INTEGER RANGE 1 TO 2;
BEGIN
PROCESS(clk4)
BEGIN
    IF (clk4'EVENT AND clk4='1') THEN
        IF(nI=2) THEN
			nI<=1;
			q<=NOT q;
			ELSIF(nI<2) THEN
			    nI<=nI+1;
				ELSIF(nI=1) THEN
					q<=NOT q;		
		END IF;
	Q4<=q;
    END IF;
END PROCESS;
END behav;