ad0809.txt

关于EDA编程的一些程序

module ad_da(clk,wr,rd,eoc,start,data);
input clk,eoc;
output wr,rd,start;
//output[2:0] addr;
inout[7:0] data;

reg rd,wr,start;
reg[2:0] st;
reg[7:0] d;

//wire[7:0] d=eoc?data:d;
wire[7:0] data=!wr?d:8'hzz;
//wire[2:0] addr=0;
//wire oe=eoc;

always @(posedge clk)
begin
  st=st+1;
end

always @(posedge clk)
begin
  case(st)
  0:wr=1;
  1:rd=eoc?1:0;
  2:if(rd) begin d=data;start=1;end
  3:begin rd=0;start=0;end
  4:wr=0;
  endcase
end

endmodule