mcu.txt

关于EDA编程的一些程序

module w1(clk,data,addr);
input clk;
inout[7:0] data;
output[7:0] addr;

reg rd;
reg[7:0] pc;
reg[7:0] data_reg,addr;
reg[7:0] reg0,reg1;

wire[7:0] data=rd?data_reg:8'hzz;

always @(negedge clk)
begin
  rd=(addr[7:6]==3)?1:0; 
end

always @(posedge clk)
begin
  pc=pc+1; 
end

always @(posedge clk)
begin
  case(pc) 
  0:addr=8'h0f;
  1:addr=8'h40;
  2:addr=8'h80;
  3:addr=8'h01;
  4:addr=8'hc0;
  endcase
end

always @(negedge clk)
begin
  if     (addr==8'h40) reg0=data;
  else if(addr==8'hc0) data_reg=reg0;

  else if(addr==8'h00) reg0=data_reg;
  else if(addr==8'h01) reg1=data_reg;
  else if(addr==8'h80) data_reg=reg0;
  else if(addr==8'h81) data_reg=reg1;
end

endmodule