幅值检测.txt

关于EDA编程的一些程序

module w1(clk,din,dout);
input  clk;
input  din;                 //input stdio wave
output dout;                //output half of input to max value

reg dout,din_;
reg[23:0] count1;
reg[22:0] count2,count3,count4;

always @(posedge clk)
begin
  din_<=din;
  case({din_,din})
  0:count1=0;
  1:count3=count2;
  2:count2=count1[23:1];
  3:count1=count1+1;
  endcase
end

always @(posedge clk)
begin
  if(din&&(count2!=0))
    if(count1[15])
      if(count1[23:6]=={1'b0,count2[22:6]}) 
        if(count1[23:6]=={1'b0,count3[22:6]})
          dout=0;
        else ;
      else ;
    else
      if(count1[23:2]=={1'b0,count2[22:2]}) 
        if(count1[23:2]=={1'b0,count3[22:2]})
          dout=0;
        else ;
      else ;
  else dout=1;
end

endmodule