sj.txt

关于EDA编程的一些程序

module w2(clk,data,wr,rd,ale,cs,into,led,rxd,txd);
input wr,rd,cs,ale;
input clk,rxd;
output txd;
output into;
inout[7:0] data;
output[7:0] led;

reg[7:0] d_reg;
reg[7:0] led;                  //use of test
reg[7:0] d_txd,d_rxd;

wire rd_=!cs?~rd:0;
wire wr_=!cs?~wr:0;
wire[7:0] addr=ale?data:addr;
wire[7:0] data=rd_?d_reg:8'hzz;
//wire into=0;

always @(posedge wr_) 
begin
  case(addr)
  0:led=data;
  1:d_txd=data;
  default:;
  endcase
end

always @(posedge rd_)
begin
  case(addr)
  0:d_reg=led;
  1:d_reg=d_rxd;
  default:;
  endcase
end

rs232_send send(clk,txd,d_txd,wr);
rs232_receive receive(clk,rxd,d_rxd,into);

endmodule
//------------------------------------------------------------------

module rs232_send(clk,txd,din,wr);  //send data to rs232
input clk,wr;
input[7:0] din;
output txd;

reg bt_cp,wr_1,wr_2,wr_3;
reg[3:0] txd_st;               //the staute of sending
reg[9:0] bt;                   //the speed of every bit to rs232
reg txd;

always @(posedge clk)
begin
  if({wr_1,wr}==2) wr_2=~wr_2;
  wr_1<=wr;
  bt=(bt!=575)?bt+1:0;          //edit speed  19200 bit/s
  bt_cp=(bt==575)?1:0;
end

always @(posedge bt_cp)
begin
  case(txd_st)
  0:txd_st=(wr_2!=wr_3)?1:0;
  1:begin txd_st=2;txd=0;end
  2:begin txd_st=3;txd=din[0];end
  3:begin txd_st=4;txd=din[1];end
  4:begin txd_st=5;txd=din[2];end
  5:begin txd_st=6;txd=din[3];end
  6:begin txd_st=7;txd=din[4];end
  7:begin txd_st=8;txd=din[5];end
  8:begin txd_st=9;txd=din[6];end
  9:begin txd_st=10;txd=din[7];end
 10:begin txd_st=11;txd=1;end
  default:begin txd_st=0;txd=1;end
  endcase
  wr_3<=wr_2;
end

endmodule
//----------------------------------------------------------------------

module rs232_receive(clk,rxd,dout,into);  //receive data from rs232
input clk,rxd;
output into;
output[7:0] dout;

reg bt_cp,cy_cp,into;
reg[3:0] rxd_st;                        //the staute of receiving
reg[2:0] cy_st;                         //1/8 time using  
reg[9:0] bt;                            //the speed of every bit to rs232
reg[7:0] dout;

always @(posedge clk)
begin
  bt=(bt!=71)?bt+1:0;                   //edit speed  19200 bit/s
  bt_cp=(bt==71)?1:0;  
end

always @(posedge bt_cp)
begin
  if((rxd==1)&&(rxd_st==0)) cy_st=0;
  else cy_st=cy_st+1;
  cy_cp=(cy_st==4)?1:0;                      //the forth clect point
end

always @(posedge cy_cp)
begin
  case(rxd_st)
  0:begin rxd_st=(rxd==0)?1:0;into=1;end
  1:begin rxd_st=2;dout[0]=rxd;end
  2:begin rxd_st=3;dout[1]=rxd;end
  3:begin rxd_st=4;dout[2]=rxd;end
  4:begin rxd_st=5;dout[3]=rxd;end
  5:begin rxd_st=6;dout[4]=rxd;end
  6:begin rxd_st=7;dout[5]=rxd;end
  7:begin rxd_st=8;dout[6]=rxd;end
  8:begin rxd_st=0;dout[7]=rxd;into=0;end
  default:rxd_st=0;
  endcase
end

endmodule