浮点减法.txt

关于EDA编程的一些程序

module w2(a,b,c);
input[23:0] a,b;
output[23:0] c;

wire[15:0] b1=~b[15:0]+1; 
wire[23:0] b_={b[23:16],b1};
addf sub(a,b_,c);

endmodule

//-------------------------------------------------------------------
module addf(d1,d2,d3);
input[23:0] d1,d2;
output[23:0] d3;

integer i;
reg sd;
reg[7:0] s,s_,e;
reg[23:0] d3;
reg[31:0] dd1,dd2,ddw,dd;

wire[31:0] dw1={1'h0,d1[14:0],16'h0000};
wire[31:0] dw2={1'h0,d2[14:0],16'h0000};
wire[31:0] d=dd1+dd2;

always 
begin
  s=d1[23:16]-d2[23:16];
  if(s[7]) begin 
    s_=~s-1;
    ddw=dw1;
    dd1=dd;
    dd2=dw2;
    e=d2[23:16];
  end
  else  begin 
    s_=s;
    ddw=dw2;
    dd2=dd;
    dd1=dw1;
    e=d1[23:16];
  end  
end

always
begin
  sd=d1[15]|d2[15];
  if((d1[14:0]==0)&&(d2[14:0]==0)) d3=0;
  else begin
       if(d[31:16]==0) d3={e-15,sd,d[15: 1]};
  else if(d[31:17]==0) d3={e-14,sd,d[16: 2]};
  else if(d[31:18]==0) d3={e-13,sd,d[17: 3]};
  else if(d[31:19]==0) d3={e-12,sd,d[18: 4]};
  else if(d[31:20]==0) d3={e-11,sd,d[19: 5]};
  else if(d[31:21]==0) d3={e-10,sd,d[20: 6]};
  else if(d[31:22]==0) d3={e- 9,sd,d[21: 7]};
  else if(d[31:23]==0) d3={e- 8,sd,d[22: 8]};
  else if(d[31:24]==0) d3={e- 7,sd,d[23: 9]};
  else if(d[31:25]==0) d3={e- 6,sd,d[24:10]};
  else if(d[31:26]==0) d3={e- 5,sd,d[25:11]};
  else if(d[31:27]==0) d3={e- 4,sd,d[26:12]};
  else if(d[31:28]==0) d3={e- 3,sd,d[27:13]};
  else if(d[31:29]==0) d3={e- 2,sd,d[28:14]};
  else if(d[31:30]==0) d3={e- 1,sd,d[29:15]};
  else if(d[31]==0)    d3={e   ,sd,d[30:16]};
  else 
  begin
    if({d1[15],d2[15]}==3) d3={e+1 ,1'b1,d[31:17]};
    else if({d1[15],d2[15]}==0) d3={e+1 ,1'b0,d[31:17]};
    else d3={e,1'b0,d[30:16]};
  end
  //d3={e,d[31:16]};
  end
end

always 
begin
   i=s_;
   dd=ddw>>i;
/*  case(s_)
   0:dd=ddw>> 0;
   1:dd=ddw>> 1;
   2:dd=ddw>> 2;
   3:dd=ddw>> 3;
   4:dd=ddw>> 4;
   5:dd=ddw>> 5;
   6:dd=ddw>> 6;
   7:dd=ddw>> 7;
   8:dd=ddw>> 8;
   9:dd=ddw>> 9;
  10:dd=ddw>>10;
  11:dd=ddw>>11;
  12:dd=ddw>>12;
  13:dd=ddw>>13;
  14:dd=ddw>>14;
  15:dd=ddw>>15;
  16:dd=ddw>>16;
  17:dd=ddw>>17;
  18:dd=ddw>>18;
  19:dd=ddw>>19;
  20:dd=ddw>>20;
  21:dd=ddw>>21;
  22:dd=ddw>>22;
  23:dd=ddw>>23;
  24:dd=ddw>>24;
  25:dd=ddw>>25;
  26:dd=ddw>>26;
  27:dd=ddw>>27;
  28:dd=ddw>>28;
  29:dd=ddw>>29;
  30:dd=ddw>>30;
  31:dd=ddw>>31;
  default:dd=0;
  endcase*/
end

endmodule