i2c_altera.tan.qmsg

来自「filter,很不错,大家可以看以下」· QMSG 代码 · 共 13 行 · 第 1/5 页

{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'SYSCLK' 14 " "Warning: Can't achieve timing requirement Clock Setup: 'SYSCLK' along 14 path(s). See Report window for details." {  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "PCLK memory add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|ram_block1a0~porta_address_reg0 register add_mask:inst22\|data4byte\[8\] 101.56 MHz 9.846 ns Internal " "Info: Clock \"PCLK\" has Internal fmax of 101.56 MHz between source memory \"add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|ram_block1a0~porta_address_reg0\" and destination register \"add_mask:inst22\|data4byte\[8\]\" (period= 9.846 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.148 ns + Longest memory register " "Info: + Longest memory to register delay is 9.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M4K_X17_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X17_Y8; Fanout = 1; MEM Node = 'add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_j1t.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_j1t.tdf" 48 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|ram_block1a0 2 MEM M4K_X17_Y8 1 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X17_Y8; Fanout = 1; MEM Node = 'add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|ram_block1a0'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "4.308 ns" { add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0 } "NODE_NAME" } "" } } { "db/altsyncram_j1t.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_j1t.tdf" 48 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.475 ns) + CELL(0.442 ns) 6.225 ns add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|mux_rab:mux2\|w_result42w~44 3 COMB LC_X20_Y7_N3 1 " "Info: 3: + IC(1.475 ns) + CELL(0.442 ns) = 6.225 ns; Loc. = LC_X20_Y7_N3; Fanout = 1; COMB Node = 'add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|mux_rab:mux2\|w_result42w~44'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "1.917 ns" { add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~44 } "NODE_NAME" } "" } } { "db/mux_rab.tdf" "" { Text "D:/VieoColorBar/Proj/db/mux_rab.tdf" 33 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.421 ns) + CELL(0.114 ns) 6.760 ns add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|mux_rab:mux2\|w_result42w~45 4 COMB LC_X20_Y7_N0 32 " "Info: 4: + IC(0.421 ns) + CELL(0.114 ns) = 6.760 ns; Loc. = LC_X20_Y7_N0; Fanout = 32; COMB Node = 'add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|mux_rab:mux2\|w_result42w~45'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "0.535 ns" { add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~44 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~45 } "NODE_NAME" } "" } } { "db/mux_rab.tdf" "" { Text "D:/VieoColorBar/Proj/db/mux_rab.tdf" 33 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.650 ns) + CELL(0.738 ns) 9.148 ns add_mask:inst22\|data4byte\[8\] 5 REG LC_X23_Y9_N4 1 " "Info: 5: + IC(1.650 ns) + CELL(0.738 ns) = 9.148 ns; Loc. = LC_X23_Y9_N4; Fanout = 1; REG Node = 'add_mask:inst22\|data4byte\[8\]'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.388 ns" { add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~45 add_mask:inst22|data4byte[8] } "NODE_NAME" } "" } } { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 127 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.602 ns 61.24 % " "Info: Total cell delay = 5.602 ns ( 61.24 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.546 ns 38.76 % " "Info: Total interconnect delay = 3.546 ns ( 38.76 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "9.148 ns" { add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~44 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~45 add_mask:inst22|data4byte[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.148 ns" { add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~44 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~45 add_mask:inst22|data4byte[8] } { 0.000ns 0.000ns 1.475ns 0.421ns 1.650ns } { 0.000ns 4.308ns 0.442ns 0.114ns 0.738ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.011 ns - Smallest " "Info: - Smallest clock skew is -0.011 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PCLK destination 2.910 ns + Shortest register " "Info: + Shortest clock path from clock \"PCLK\" to destination register is 2.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns PCLK 1 CLK PIN_29 257 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 257; CLK Node = 'PCLK'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { PCLK } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1512 1696 1864 1528 "PCLK" "" } { 1256 2064 2144 1272 "PCLK" "" } { 1272 1736 1832 1288 "PCLK" "" } { 1248 1456 1520 1264 "PCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.711 ns) 2.910 ns add_mask:inst22\|data4byte\[8\] 2 REG LC_X23_Y9_N4 1 " "Info: 2: + IC(0.730 ns) + CELL(0.711 ns) = 2.910 ns; Loc. = LC_X23_Y9_N4; Fanout = 1; REG Node = 'add_mask:inst22\|data4byte\[8\]'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "1.441 ns" { PCLK add_mask:inst22|data4byte[8] } "NODE_NAME" } "" } } { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 127 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.91 % " "Info: Total cell delay = 2.180 ns ( 74.91 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 25.09 % " "Info: Total interconnect delay = 0.730 ns ( 25.09 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.910 ns" { PCLK add_mask:inst22|data4byte[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { PCLK PCLK~out0 add_mask:inst22|data4byte[8] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PCLK source 2.921 ns - Longest memory " "Info: - Longest clock path from clock \"PCLK\" to source memory is 2.921 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns PCLK 1 CLK PIN_29 257 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 257; CLK Node = 'PCLK'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { PCLK } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1512 1696 1864 1528 "PCLK" "" } { 1256 2064 2144 1272 "PCLK" "" } { 1272 1736 1832 1288 "PCLK" "" } { 1248 1456 1520 1264 "PCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.722 ns) 2.921 ns add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|ram_block1a0~porta_address_reg0 2 MEM M4K_X17_Y8 1 " "Info: 2: + IC(0.730 ns) + CELL(0.722 ns) = 2.921 ns; Loc. = M4K_X17_Y8; Fanout = 1; MEM Node = 'add_mask:inst22\|mask_rom:mask_rom0\|altsyncram:altsyncram_component\|altsyncram_j1t:auto_generated\|ram_block1a0~porta_address_reg0'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "1.452 ns" { PCLK add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "db/altsyncram_j1t.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_j1t.tdf" 48 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 75.01 % " "Info: Total cell delay = 2.191 ns ( 75.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.730 ns 24.99 % " "Info: Total interconnect delay = 0.730 ns ( 24.99 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.921 ns" { PCLK add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.921 ns" { PCLK PCLK~out0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.910 ns" { PCLK add_mask:inst22|data4byte[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { PCLK PCLK~out0 add_mask:inst22|data4byte[8] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.921 ns" { PCLK add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.921 ns" { PCLK PCLK~out0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_j1t.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_j1t.tdf" 48 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "add_mask.v" "" { Text "D:/VieoColorBar/Proj/add_mask.v" 127 -1 0 } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "9.148 ns" { add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~44 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~45 add_mask:inst22|data4byte[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "9.148 ns" { add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~44 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|mux_rab:mux2|w_result42w~45 add_mask:inst22|data4byte[8] } { 0.000ns 0.000ns 1.475ns 0.421ns 1.650ns } { 0.000ns 4.308ns 0.442ns 0.114ns 0.738ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.910 ns" { PCLK add_mask:inst22|data4byte[8] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.910 ns" { PCLK PCLK~out0 add_mask:inst22|data4byte[8] } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.921 ns" { PCLK add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.921 ns" { PCLK PCLK~out0 add_mask:inst22|mask_rom:mask_rom0|altsyncram:altsyncram_component|altsyncram_j1t:auto_generated|ram_block1a0~porta_address_reg0 } { 0.000ns 0.000ns 0.730ns } { 0.000ns 1.469ns 0.722ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "PLL:inst26\|altpll:altpll_component\|_clk0 register i2c_cmd:inst\|execute register i2c_cmd:inst\|execute 822 ps " "Info: Minimum slack time is 822 ps for clock \"PLL:inst26\|altpll:altpll_component\|_clk0\" between source register \"i2c_cmd:inst\|execute\" and destination register \"i2c_cmd:inst\|execute\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.613 ns + Shortest register register " "Info: + Shortest register to register delay is 0.613 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_cmd:inst\|execute 1 REG LC_X20_Y14_N4 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y14_N4; Fanout = 8; REG Node = 'i2c_cmd:inst\|execute'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.613 ns) 0.613 ns i2c_cmd:inst\|execute 2 REG LC_X20_Y14_N4 8 " "Info: 2: + IC(0.000 ns) + CELL(0.613 ns) = 0.613 ns; Loc. = LC_X20_Y14_N4; Fanout = 8; REG Node = 'i2c_cmd:inst\|execute'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "0.613 ns" { i2c_cmd:inst|execute i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.613 ns 100.00 % " "Info: Total cell delay = 0.613 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "0.613 ns" { i2c_cmd:inst|execute i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.613 ns" { i2c_cmd:inst|execute i2c_cmd:inst|execute } { 0.0ns 0.0ns } { 0.0ns 0.613ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -0.323 ns " "Info: + Latch edge is -0.323 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL:inst26\|altpll:altpll_component\|_clk0 12.500 ns -0.323 ns  50 " "Info: Clock period of Destination clock \"PLL:inst26\|altpll:altpll_component\|_clk0\" is 12.500 ns with  offset of -0.323 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -0.323 ns " "Info: - Launch edge is -0.323 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:inst26\|altpll:altpll_component\|_clk0 12.500 ns -0.323 ns  50 " "Info: Clock period of Source clock \"PLL:inst26\|altpll:altpll_component\|_clk0\" is 12.500 ns with  offset of -0.323 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst26\|altpll:altpll_component\|_clk0 destination 6.865 ns + Longest register " "Info: + Longest clock path from clock \"PLL:inst26\|altpll:altpll_component\|_clk0\" to destination register is 6.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst26\|altpll:altpll_component\|_clk0 1 CLK PLL_2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 3; CLK Node = 'PLL:inst26\|altpll:altpll_component\|_clk0'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { PLL:inst26|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.935 ns) 2.609 ns clk_gen:inst19\|clkout 2 REG LC_X27_Y10_N2 148 " "Info: 2: + IC(1.674 ns) + CELL(0.935 ns) = 2.609 ns; Loc. = LC_X27_Y10_N2; Fanout = 148; REG Node = 'clk_gen:inst19\|clkout'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.609 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout } "NODE_NAME" } "" } } { "clk_gen.v" "" { Text "D:/VieoColorBar/Proj/clk_gen.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.545 ns) + CELL(0.711 ns) 6.865 ns i2c_cmd:inst\|execute 3 REG LC_X20_Y14_N4 8 " "Info: 3: + IC(3.545 ns) + CELL(0.711 ns) = 6.865 ns; Loc. = LC_X20_Y14_N4; Fanout = 8; REG Node = 'i2c_cmd:inst\|execute'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "4.256 ns" { clk_gen:inst19|clkout i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 23.98 % " "Info: Total cell delay = 1.646 ns ( 23.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.219 ns 76.02 % " "Info: Total interconnect delay = 5.219 ns ( 76.02 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } { 0.0ns 1.674ns 3.545ns } { 0.0ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst26\|altpll:altpll_component\|_clk0 source 6.865 ns - Shortest register " "Info: - Shortest clock path from clock \"PLL:inst26\|altpll:altpll_component\|_clk0\" to source register is 6.865 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst26\|altpll:altpll_component\|_clk0 1 CLK PLL_2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 3; CLK Node = 'PLL:inst26\|altpll:altpll_component\|_clk0'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { PLL:inst26|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.935 ns) 2.609 ns clk_gen:inst19\|clkout 2 REG LC_X27_Y10_N2 148 " "Info: 2: + IC(1.674 ns) + CELL(0.935 ns) = 2.609 ns; Loc. = LC_X27_Y10_N2; Fanout = 148; REG Node = 'clk_gen:inst19\|clkout'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.609 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout } "NODE_NAME" } "" } } { "clk_gen.v" "" { Text "D:/VieoColorBar/Proj/clk_gen.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.545 ns) + CELL(0.711 ns) 6.865 ns i2c_cmd:inst\|execute 3 REG LC_X20_Y14_N4 8 " "Info: 3: + IC(3.545 ns) + CELL(0.711 ns) = 6.865 ns; Loc. = LC_X20_Y14_N4; Fanout = 8; REG Node = 'i2c_cmd:inst\|execute'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "4.256 ns" { clk_gen:inst19|clkout i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 23.98 % " "Info: Total cell delay = 1.646 ns ( 23.98 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.219 ns 76.02 % " "Info: Total interconnect delay = 5.219 ns ( 76.02 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } { 0.0ns 1.674ns 3.545ns } { 0.0ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } { 0.0ns 1.674ns 3.545ns } { 0.0ns 0.935ns 0.711ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } { 0.0ns 1.674ns 3.545ns } { 0.0ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 9 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 9 -1 0 } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } { 0.0ns 1.674ns 3.545ns } { 0.0ns 0.935ns 0.711ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } { 0.0ns 1.674ns 3.545ns } { 0.0ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "0.613 ns" { i2c_cmd:inst|execute i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.613 ns" { i2c_cmd:inst|execute i2c_cmd:inst|execute } { 0.0ns 0.0ns } { 0.0ns 0.613ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } { 0.0ns 1.674ns 3.545ns } { 0.0ns 0.935ns 0.711ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.865 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|execute } { 0.0ns 1.674ns 3.545ns } { 0.0ns 0.935ns 0.711ns } } }  } 0}