i2c_altera.tan.qmsg

来自「filter,很不错,大家可以看以下」· QMSG 代码 · 共 13 行 · 第 1/5 页

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "PLL:inst26\|altpll:altpll_component\|_clk0 register filter:inst8\|rst_out register i2c_cmd:inst\|i2c_data_t\[7\] 1.09 ns " "Info: Slack time is 1.09 ns for clock \"PLL:inst26\|altpll:altpll_component\|_clk0\" between source register \"filter:inst8\|rst_out\" and destination register \"i2c_cmd:inst\|i2c_data_t\[7\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "4.068 ns + Largest register register " "Info: + Largest register to register requirement is 4.068 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "2.177 ns + " "Info: + Setup relationship between source and destination is 2.177 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 2.177 ns " "Info: + Latch edge is 2.177 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination PLL:inst26\|altpll:altpll_component\|_clk0 12.500 ns -0.323 ns  50 " "Info: Clock period of Destination clock \"PLL:inst26\|altpll:altpll_component\|_clk0\" is 12.500 ns with  offset of -0.323 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source SYSCLK 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"SYSCLK\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "2.152 ns + Largest " "Info: + Largest clock skew is 2.152 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst26\|altpll:altpll_component\|_clk0 destination 6.826 ns + Shortest register " "Info: + Shortest clock path from clock \"PLL:inst26\|altpll:altpll_component\|_clk0\" to destination register is 6.826 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst26\|altpll:altpll_component\|_clk0 1 CLK PLL_2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 3; CLK Node = 'PLL:inst26\|altpll:altpll_component\|_clk0'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { PLL:inst26|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.935 ns) 2.609 ns clk_gen:inst19\|clkout 2 REG LC_X27_Y10_N2 148 " "Info: 2: + IC(1.674 ns) + CELL(0.935 ns) = 2.609 ns; Loc. = LC_X27_Y10_N2; Fanout = 148; REG Node = 'clk_gen:inst19\|clkout'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.609 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout } "NODE_NAME" } "" } } { "clk_gen.v" "" { Text "D:/VieoColorBar/Proj/clk_gen.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.506 ns) + CELL(0.711 ns) 6.826 ns i2c_cmd:inst\|i2c_data_t\[7\] 3 REG LC_X16_Y12_N5 2 " "Info: 3: + IC(3.506 ns) + CELL(0.711 ns) = 6.826 ns; Loc. = LC_X16_Y12_N5; Fanout = 2; REG Node = 'i2c_cmd:inst\|i2c_data_t\[7\]'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "4.217 ns" { clk_gen:inst19|clkout i2c_cmd:inst|i2c_data_t[7] } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 24.11 % " "Info: Total cell delay = 1.646 ns ( 24.11 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.180 ns 75.89 % " "Info: Total interconnect delay = 5.180 ns ( 75.89 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.826 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|i2c_data_t[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.826 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|i2c_data_t[7] } { 0.000ns 1.674ns 3.506ns } { 0.000ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK source 4.674 ns - Longest register " "Info: - Longest clock path from clock \"SYSCLK\" to source register is 4.674 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYSCLK 1 CLK PIN_153 71 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 71; CLK Node = 'SYSCLK'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { SYSCLK } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1424 200 368 1440 "SYSCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.935 ns) 3.186 ns filter:inst8\|cnt\[15\] 2 REG LC_X21_Y13_N7 2 " "Info: 2: + IC(0.782 ns) + CELL(0.935 ns) = 3.186 ns; Loc. = LC_X21_Y13_N7; Fanout = 2; REG Node = 'filter:inst8\|cnt\[15\]'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "1.717 ns" { SYSCLK filter:inst8|cnt[15] } "NODE_NAME" } "" } } { "filter.v" "" { Text "D:/VieoColorBar/Proj/filter.v" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.777 ns) + CELL(0.711 ns) 4.674 ns filter:inst8\|rst_out 3 REG LC_X20_Y13_N8 138 " "Info: 3: + IC(0.777 ns) + CELL(0.711 ns) = 4.674 ns; Loc. = LC_X20_Y13_N8; Fanout = 138; REG Node = 'filter:inst8\|rst_out'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "1.488 ns" { filter:inst8|cnt[15] filter:inst8|rst_out } "NODE_NAME" } "" } } { "filter.v" "" { Text "D:/VieoColorBar/Proj/filter.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 66.65 % " "Info: Total cell delay = 3.115 ns ( 66.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.559 ns 33.35 % " "Info: Total interconnect delay = 1.559 ns ( 33.35 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "4.674 ns" { SYSCLK filter:inst8|cnt[15] filter:inst8|rst_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.674 ns" { SYSCLK SYSCLK~out0 filter:inst8|cnt[15] filter:inst8|rst_out } { 0.000ns 0.000ns 0.782ns 0.777ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.826 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|i2c_data_t[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.826 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|i2c_data_t[7] } { 0.000ns 1.674ns 3.506ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "4.674 ns" { SYSCLK filter:inst8|cnt[15] filter:inst8|rst_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.674 ns" { SYSCLK SYSCLK~out0 filter:inst8|cnt[15] filter:inst8|rst_out } { 0.000ns 0.000ns 0.782ns 0.777ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "filter.v" "" { Text "D:/VieoColorBar/Proj/filter.v" 3 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 11 -1 0 } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.826 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|i2c_data_t[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.826 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|i2c_data_t[7] } { 0.000ns 1.674ns 3.506ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "4.674 ns" { SYSCLK filter:inst8|cnt[15] filter:inst8|rst_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.674 ns" { SYSCLK SYSCLK~out0 filter:inst8|cnt[15] filter:inst8|rst_out } { 0.000ns 0.000ns 0.782ns 0.777ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.978 ns - Longest register register " "Info: - Longest register to register delay is 2.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns filter:inst8\|rst_out 1 REG LC_X20_Y13_N8 138 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y13_N8; Fanout = 138; REG Node = 'filter:inst8\|rst_out'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { filter:inst8|rst_out } "NODE_NAME" } "" } } { "filter.v" "" { Text "D:/VieoColorBar/Proj/filter.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.866 ns) + CELL(1.112 ns) 2.978 ns i2c_cmd:inst\|i2c_data_t\[7\] 2 REG LC_X16_Y12_N5 2 " "Info: 2: + IC(1.866 ns) + CELL(1.112 ns) = 2.978 ns; Loc. = LC_X16_Y12_N5; Fanout = 2; REG Node = 'i2c_cmd:inst\|i2c_data_t\[7\]'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.978 ns" { filter:inst8|rst_out i2c_cmd:inst|i2c_data_t[7] } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 11 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.112 ns 37.34 % " "Info: Total cell delay = 1.112 ns ( 37.34 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.866 ns 62.66 % " "Info: Total interconnect delay = 1.866 ns ( 62.66 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.978 ns" { filter:inst8|rst_out i2c_cmd:inst|i2c_data_t[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.978 ns" { filter:inst8|rst_out i2c_cmd:inst|i2c_data_t[7] } { 0.000ns 1.866ns } { 0.000ns 1.112ns } } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.826 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|i2c_data_t[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.826 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|i2c_data_t[7] } { 0.000ns 1.674ns 3.506ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "4.674 ns" { SYSCLK filter:inst8|cnt[15] filter:inst8|rst_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.674 ns" { SYSCLK SYSCLK~out0 filter:inst8|cnt[15] filter:inst8|rst_out } { 0.000ns 0.000ns 0.782ns 0.777ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.978 ns" { filter:inst8|rst_out i2c_cmd:inst|i2c_data_t[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.978 ns" { filter:inst8|rst_out i2c_cmd:inst|i2c_data_t[7] } { 0.000ns 1.866ns } { 0.000ns 1.112ns } } }  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "SYSCLK register i2c_cmd:inst\|rom_addr\[5\] memory SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_5qp:auto_generated\|ram_block1a7~porta_address_reg5 -5.705 ns " "Info: Slack time is -5.705 ns for clock \"SYSCLK\" between source register \"i2c_cmd:inst\|rom_addr\[5\]\" and destination memory \"SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_5qp:auto_generated\|ram_block1a7~porta_address_reg5\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-3.877 ns + Largest register memory " "Info: + Largest register to memory requirement is -3.877 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "0.323 ns + " "Info: + Setup relationship between source and destination is 0.323 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 2.500 ns " "Info: + Latch edge is 2.500 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination SYSCLK 20.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"SYSCLK\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 2.177 ns " "Info: - Launch edge is 2.177 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source PLL:inst26\|altpll:altpll_component\|_clk0 12.500 ns -0.323 ns  50 " "Info: Clock period of Source clock \"PLL:inst26\|altpll:altpll_component\|_clk0\" is 12.500 ns with  offset of -0.323 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.883 ns + Largest " "Info: + Largest clock skew is -3.883 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK destination 2.973 ns + Shortest memory " "Info: + Shortest clock path from clock \"SYSCLK\" to destination memory is 2.973 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns SYSCLK 1 CLK PIN_153 71 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 71; CLK Node = 'SYSCLK'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { SYSCLK } "NODE_NAME" } "" } } { "I2C_ALTERA.bdf" "" { Schematic "D:/VieoColorBar/Proj/I2C_ALTERA.bdf" { { 1424 200 368 1440 "SYSCLK" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.722 ns) 2.973 ns SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_5qp:auto_generated\|ram_block1a7~porta_address_reg5 2 MEM M4K_X17_Y14 8 " "Info: 2: + IC(0.782 ns) + CELL(0.722 ns) = 2.973 ns; Loc. = M4K_X17_Y14; Fanout = 8; MEM Node = 'SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_5qp:auto_generated\|ram_block1a7~porta_address_reg5'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "1.504 ns" { SYSCLK SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "db/altsyncram_5qp.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_5qp.tdf" 174 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 73.70 % " "Info: Total cell delay = 2.191 ns ( 73.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns 26.30 % " "Info: Total interconnect delay = 0.782 ns ( 26.30 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.973 ns" { SYSCLK SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.973 ns" { SYSCLK SYSCLK~out0 SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "PLL:inst26\|altpll:altpll_component\|_clk0 source 6.856 ns - Longest register " "Info: - Longest clock path from clock \"PLL:inst26\|altpll:altpll_component\|_clk0\" to source register is 6.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns PLL:inst26\|altpll:altpll_component\|_clk0 1 CLK PLL_2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_2; Fanout = 3; CLK Node = 'PLL:inst26\|altpll:altpll_component\|_clk0'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { PLL:inst26|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.935 ns) 2.609 ns clk_gen:inst19\|clkout 2 REG LC_X27_Y10_N2 148 " "Info: 2: + IC(1.674 ns) + CELL(0.935 ns) = 2.609 ns; Loc. = LC_X27_Y10_N2; Fanout = 148; REG Node = 'clk_gen:inst19\|clkout'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.609 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout } "NODE_NAME" } "" } } { "clk_gen.v" "" { Text "D:/VieoColorBar/Proj/clk_gen.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.536 ns) + CELL(0.711 ns) 6.856 ns i2c_cmd:inst\|rom_addr\[5\] 3 REG LC_X15_Y14_N6 7 " "Info: 3: + IC(3.536 ns) + CELL(0.711 ns) = 6.856 ns; Loc. = LC_X15_Y14_N6; Fanout = 7; REG Node = 'i2c_cmd:inst\|rom_addr\[5\]'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "4.247 ns" { clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[5] } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 24.01 % " "Info: Total cell delay = 1.646 ns ( 24.01 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.210 ns 75.99 % " "Info: Total interconnect delay = 5.210 ns ( 75.99 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.856 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.856 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[5] } { 0.000ns 1.674ns 3.536ns } { 0.000ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.973 ns" { SYSCLK SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.973 ns" { SYSCLK SYSCLK~out0 SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.856 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.856 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[5] } { 0.000ns 1.674ns 3.536ns } { 0.000ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 10 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_5qp.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_5qp.tdf" 174 2 0 } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.973 ns" { SYSCLK SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.973 ns" { SYSCLK SYSCLK~out0 SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.856 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.856 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[5] } { 0.000ns 1.674ns 3.536ns } { 0.000ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.828 ns - Longest register memory " "Info: - Longest register to memory delay is 1.828 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c_cmd:inst\|rom_addr\[5\] 1 REG LC_X15_Y14_N6 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X15_Y14_N6; Fanout = 7; REG Node = 'i2c_cmd:inst\|rom_addr\[5\]'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "" { i2c_cmd:inst|rom_addr[5] } "NODE_NAME" } "" } } { "i2c_cmd.v" "" { Text "D:/VieoColorBar/Proj/i2c_cmd.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.445 ns) + CELL(0.383 ns) 1.828 ns SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_5qp:auto_generated\|ram_block1a7~porta_address_reg5 2 MEM M4K_X17_Y14 8 " "Info: 2: + IC(1.445 ns) + CELL(0.383 ns) = 1.828 ns; Loc. = M4K_X17_Y14; Fanout = 8; MEM Node = 'SAA_ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_5qp:auto_generated\|ram_block1a7~porta_address_reg5'" {  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "1.828 ns" { i2c_cmd:inst|rom_addr[5] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "db/altsyncram_5qp.tdf" "" { Text "D:/VieoColorBar/Proj/db/altsyncram_5qp.tdf" 174 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns 20.95 % " "Info: Total cell delay = 0.383 ns ( 20.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.445 ns 79.05 % " "Info: Total interconnect delay = 1.445 ns ( 79.05 % )" {  } {  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "1.828 ns" { i2c_cmd:inst|rom_addr[5] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.828 ns" { i2c_cmd:inst|rom_addr[5] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } { 0.000ns 1.445ns } { 0.000ns 0.383ns } } }  } 0}  } { { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "2.973 ns" { SYSCLK SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.973 ns" { SYSCLK SYSCLK~out0 SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.722ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "6.856 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.856 ns" { PLL:inst26|altpll:altpll_component|_clk0 clk_gen:inst19|clkout i2c_cmd:inst|rom_addr[5] } { 0.000ns 1.674ns 3.536ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" "" { Report "D:/VieoColorBar/Proj/db/I2C_ALTERA_cmp.qrpt" Compiler "I2C_ALTERA" "UNKNOWN" "V1" "D:/VieoColorBar/Proj/db/RVDK_Sample.quartus_db" { Floorplan "D:/VieoColorBar/Proj/" "" "1.828 ns" { i2c_cmd:inst|rom_addr[5] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.828 ns" { i2c_cmd:inst|rom_addr[5] SAA_ROM:inst2|altsyncram:altsyncram_component|altsyncram_5qp:auto_generated|ram_block1a7~porta_address_reg5 } { 0.000ns 1.445ns } { 0.000ns 0.383ns } } }  } 0}