hdlc_recv.v

hdlc帧接收器 包含文件： 设计代码 测试代码 综合脚步 说明文档

////////////////////////////////////////////////
    ///father Rev : hdlc_recv_0405.v///
    ///change     : add "error_flag" ///
////////////////////////////////////////////////
`timescale 1 ns/1 ns

module hdlc_recv(
                ihdlc_RXD,
                ihdlc_RXCLK,
                ihdlc_RESET,
                ohdlc_TXD,
                ohdlc_TXCLK,
                ohdlc_TXDS
                );

/**************************************************************************/
                     ///*** input signals define ***///
/**************************************************************************/
       input         ihdlc_RXD;
       input         ihdlc_RXCLK;
       input         ihdlc_RESET;

/**************************************************************************/
                      ///***  outputs define ***///
/**************************************************************************/
       output        ohdlc_TXCLK;
       output [7:0]  ohdlc_TXD;
       output [2:0]  ohdlc_TXDS;

       reg           ohdlc_TXCLK;
       reg    [7:0]  ohdlc_TXD;
       reg    [2:0]  ohdlc_TXDS;
       reg    [2:0]  ohdlc_TXDS_tmp;
/**************************************************************************/
                     ///*** inner signals define  ***///
/**************************************************************************/
       reg           error;          // illegal byte  detectived when equal 1
       reg           error_wire;
       reg           error_flag;
       reg           delete_zero;    // 5 "1" detectived when equal 1
       reg           delete_zero_wire;
       reg           frame_end;      // end of a normal frame
       reg           flag_7e;        // "7e" detectived when equal 1
       reg [3:0]     bit_counter;
       reg [6:0]     byte_counter;
       reg [7:0]     shifter1;
       reg [7:0]     shifter2;
       reg [2:0]     byte_rst_counter;
       reg           byte_rst_counter_start;
 
/**************************************************************************/
  ///***  5 "1"& illegal frame detectiver state machine  define ***///
/**************************************************************************/
       reg [6:0]     flagdetc_cur_state;
       reg [6:0]     flagdetc_next_state;

       parameter     idle  = 7'b000_0001,
                     flag1 = 7'b000_0010,
                     flag2 = 7'b000_0100,
                     flag3 = 7'b000_1000,
                     flag4 = 7'b001_0000,
                     flag5 = 7'b010_0000,
                     flag6 = 7'b100_0000;
                     


/**************************************************************************/
                    ///***  series shifter  ***///
/**************************************************************************/
        always  @(posedge ihdlc_RXCLK or negedge ihdlc_RESET)
               begin
                     if(!ihdlc_RESET)
                               begin
                                    shifter2[7:0] <= 8'b0;
                               end
                     else 
                               begin
                                    if(delete_zero_wire)
                                           begin
                                             shifter2[7:0]  <= shifter2[7:0];
                                           end
                                    else
                                           begin
                                             shifter2[7:0]  <= {shifter2[6:0],shifter1[7]};
                                           end
                               end
               end

        always  @(posedge ihdlc_RXCLK or negedge ihdlc_RESET)
               begin
                     if(!ihdlc_RESET)
                               begin
                                    shifter1[7:0] <= 8'b0;
                               end
                     else 
                               begin
                                    if(flag_7e)
                                           begin
                                             shifter1[7:0]  <= {shifter1[6:0],ihdlc_RXD};
                                           end
                                    else
                                           begin
                                             shifter1[7:0]  <= {shifter1[6:0],ihdlc_RXD};
                                           end
                               end
               end


/**************************************************************************/
                   ///***  "7E" detectiver  ***///
/**************************************************************************/
          always @(shifter1[7:0] or byte_counter[6:0]  or bit_counter[3:0] or byte_rst_counter_start)
                    begin
                          if(shifter1[7:0]==8'h7e)
                                    begin
                                        if(byte_counter[6:0]!=0)
                                                begin
                                                       if(bit_counter[3:0]==4'b1111||bit_counter[3:0]==4'b0111)
                                                                     flag_7e  =  1'b1;
                                                       else
                                                                     flag_7e  =  1'b0;
                                                end
                                       else 
                                                begin
                                                                     flag_7e  =  1'b1;
                                                end
                                    end
                           else 
                                    begin
                                                                     flag_7e  =  1'b0;
                                    end
                    end

/**************************************************************************/
                  ///***  detectiver state machine  ***///
/**************************************************************************/
        always @(posedge ihdlc_RXCLK or negedge ihdlc_RESET)
               begin
                    if(!ihdlc_RESET)
                         begin
                             delete_zero        <= 1'b0;
                             error              <= 1'b0;
                             flagdetc_cur_state <= idle;
                         end
                    else 
                         begin
                             flagdetc_cur_state <= flagdetc_next_state;
                             delete_zero        <= delete_zero_wire;
                             error              <= error_wire;
                         end
               end      

/*************************************************************************/
             //*** 5 "1"series & illegal frame detective ***//
/*************************************************************************/
         always @(flagdetc_cur_state or shifter1[7])
                begin
                      case (flagdetc_cur_state)
                          idle  : 
                                  begin
                                     error_wire   = 1'b0; 
                                     delete_zero_wire = 1'b0;
                                     if(shifter1[7]==1'b0) 
                                          begin
                                             flagdetc_next_state = idle;
                                          end   
                                     else
                                          begin
                                             flagdetc_next_state = flag1;
                                          end
                                  end
                          flag1 :                //////////////////////////////////1 "1"
                                  begin
                                     if(shifter1[7]==1'b1) 
                                          begin
                                             flagdetc_next_state = flag2;
                                          end   
                                     else
                                          begin
                                             flagdetc_next_state = idle;
                                          end
                                  end
                          flag2 :               //////////////////////////////////2 "1"
                                  begin
                                     if(shifter1[7]==1'b1) 
                                          begin
                                             flagdetc_next_state = flag3;
                                          end   
                                     else
                                          begin
                                             flagdetc_next_state = idle;
                                          end
                                   
                                  end
                          flag3 :              //////////////////////////////////3 "1"
                                  begin
                                     if(shifter1[7]==1'b1) 
                                          begin
                                             flagdetc_next_state = flag4;
                                          end   
                                     else
                                          begin
                                             flagdetc_next_state = idle;
                                          end
                                   
                                  end
                          flag4 :             ///////////////////////////////////4 "1"
                                  begin
                                     if(shifter1[7]==1'b1) 
                                          begin
                                             flagdetc_next_state = flag5;
                                          end   
                                     else
                                          begin
                                             flagdetc_next_state = idle;
                                          end
                                   
                                  end
                          flag5 :            ////////////////////////////////////5 "1"
                                  begin
                                     if(shifter1[7]==1'b1) 
                                          begin
                                             flagdetc_next_state = flag6;
                                          end   
                                     else
                                          begin
                                             flagdetc_next_state = idle;
                                             delete_zero_wire    = 1'b1;
                                          end
                                   
                                  end
                          flag6 :           ////////////////////////////////////6 "1" and more
                                  begin
                                     if(shifter1[7]==1'b1) 
                                          begin
                                             flagdetc_next_state = flag6;
                                             if(bit_counter==4'b1101)               //for test
                                             error_wire          = 1'b1;
                                          end   
                                     else
                                          begin
                                             flagdetc_next_state = idle;
                                             //if(bit_counter==4'b1101)
                                             error_wire          = 1'b1;  // for test
                                          end