urat.fit.summary

来自「VHDL语言编写的全功能串口模块（包含DTR」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Fri Mar 23 21:47:12 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Web Edition
Revision Name : urat
Top-level Entity Name : UART
Family : Cyclone
Device : EP1C4F324C8
Timing Models : Final
Total logic elements : 73 / 4,000 ( 2 % )
Total pins : 15 / 249 ( 6 % )
Total virtual pins : 0
Total memory bits : 0 / 78,336 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )