urat.hier_info

VHDL语言编写的全功能串口模块（包含DTR

|uart
clk => clkbaud8x.CLK
clk => div_reg[0].CLK
clk => div_reg[1].CLK
clk => div_reg[2].CLK
clk => div_reg[3].CLK
clk => div_reg[4].CLK
clk => div_reg[5].CLK
clk => div_reg[6].CLK
clk => div_reg[7].CLK
rst => div_reg[7].ACLR
rst => div_reg[6].ACLR
rst => div_reg[5].ACLR
rst => div_reg[4].ACLR
rst => div_reg[3].ACLR
rst => div_reg[2].ACLR
rst => div_reg[1].ACLR
rst => div_reg[0].ACLR
rst => div8_tras_reg[2].ACLR
rst => div8_tras_reg[1].ACLR
rst => div8_tras_reg[0].ACLR
rst => send_state[0].ACLR
rst => send_state[1].ACLR
rst => send_state[2].ACLR
rst => state_tras[0].ACLR
rst => state_tras[1].ACLR
rst => state_tras[2].ACLR
rst => state_tras[3].ACLR
rst => txd_buf[0].ACLR
rst => txd_buf[1].ACLR
rst => txd_buf[2].ACLR
rst => txd_buf[3].ACLR
rst => txd_buf[4].ACLR
rst => txd_buf[5].ACLR
rst => txd_buf[6].ACLR
rst => txd_buf[7].ACLR
rst => trasstart.ACLR
rst => txd_reg.PRESET
rst => clkbaud8x.ACLR
rxd => ~NO_FANOUT~
txd <= txd_reg.DB_MAX_OUTPUT_PORT_TYPE
en <= <GND>
clkout <= clkbaud8x.DB_MAX_OUTPUT_PORT_TYPE
out_data[0] <= txd_buf[0].DB_MAX_OUTPUT_PORT_TYPE
out_data[1] <= txd_buf[1].DB_MAX_OUTPUT_PORT_TYPE
out_data[2] <= txd_buf[2].DB_MAX_OUTPUT_PORT_TYPE
out_data[3] <= txd_buf[3].DB_MAX_OUTPUT_PORT_TYPE
out_data[4] <= txd_buf[4].DB_MAX_OUTPUT_PORT_TYPE
out_data[5] <= txd_buf[5].DB_MAX_OUTPUT_PORT_TYPE
out_data[6] <= txd_buf[6].DB_MAX_OUTPUT_PORT_TYPE
out_data[7] <= txd_buf[7].DB_MAX_OUTPUT_PORT_TYPE
key_input => txd_buf~21.OUTPUTSELECT
key_input => txd_buf~22.OUTPUTSELECT
key_input => txd_buf~23.OUTPUTSELECT
key_input => txd_buf~24.OUTPUTSELECT
key_input => txd_buf~25.OUTPUTSELECT
key_input => txd_buf~26.OUTPUTSELECT
key_input => txd_buf~27.OUTPUTSELECT
key_input => txd_buf~28.OUTPUTSELECT
key_input => state_tras[3].ENA
key_input => state_tras[2].ENA
key_input => state_tras[1].ENA
key_input => state_tras[0].ENA
key_input => send_state[2].ENA
key_input => send_state[1].ENA
key_input => send_state[0].ENA
key_input => trasstart.ENA
key_input => txd_reg.ENA