urat.fit.qmsg

VHDL语言编写的全功能串口模块（包含DTR

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.324 ns register register " "Info: Estimated most critical path is register to register delay of 4.324 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns send_state\[0\] 1 REG LAB_X20_Y13 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X20_Y13; Fanout = 8; REG Node = 'send_state\[0\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { send_state[0] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.832 ns) + CELL(0.590 ns) 1.422 ns Mux14~585 2 COMB LAB_X20_Y12 1 " "Info: 2: + IC(0.832 ns) + CELL(0.590 ns) = 1.422 ns; Loc. = LAB_X20_Y12; Fanout = 1; COMB Node = 'Mux14~585'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.422 ns" { send_state[0] Mux14~585 } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 168 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.540 ns) + CELL(0.114 ns) 2.076 ns Mux14~586 3 COMB LAB_X20_Y12 1 " "Info: 3: + IC(0.540 ns) + CELL(0.114 ns) = 2.076 ns; Loc. = LAB_X20_Y12; Fanout = 1; COMB Node = 'Mux14~586'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.654 ns" { Mux14~585 Mux14~586 } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 168 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.232 ns) + CELL(0.114 ns) 3.422 ns Mux14~587 4 COMB LAB_X21_Y11 1 " "Info: 4: + IC(1.232 ns) + CELL(0.114 ns) = 3.422 ns; Loc. = LAB_X21_Y11; Fanout = 1; COMB Node = 'Mux14~587'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.346 ns" { Mux14~586 Mux14~587 } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 168 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.593 ns) + CELL(0.309 ns) 4.324 ns txd_buf\[3\] 5 REG LAB_X21_Y11 5 " "Info: 5: + IC(0.593 ns) + CELL(0.309 ns) = 4.324 ns; Loc. = LAB_X21_Y11; Fanout = 5; REG Node = 'txd_buf\[3\]'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.902 ns" { Mux14~587 txd_buf[3] } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.127 ns ( 26.06 % ) " "Info: Total cell delay = 1.127 ns ( 26.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.197 ns ( 73.94 % ) " "Info: Total interconnect delay = 3.197 ns ( 73.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.324 ns" { send_state[0] Mux14~585 Mux14~586 Mux14~587 txd_buf[3] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 1 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 1%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x20_y9 x29_y18 " "Info: The peak interconnect region extends from location x20_y9 to location x29_y18" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "en GND " "Info: Pin en has GND driving its datain port" {  } { { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 27 -1 0 } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "en" } } } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { en } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 23 21:47:12 2007 " "Info: Processing ended: Fri Mar 23 21:47:12 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/程序/uart/urat.fit.smsg " "Info: Generated suppressed messages file E:/程序/uart/urat.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}