📄 urat.sim_ori.vwf

📁 VHDL语言编写的全功能串口模块（包含DTR
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 100000000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("clk")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("key_input")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("rst")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("rxd")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("txd")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("en")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("clkout")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("out_data")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("out_data[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "out_data";
}

SIGNAL("out_data[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "out_data";
}

SIGNAL("out_data[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "out_data";
}

SIGNAL("out_data[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "out_data";
}

SIGNAL("out_data[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "out_data";
}

SIGNAL("out_data[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "out_data";
}

SIGNAL("out_data[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "out_data";
}

SIGNAL("out_data[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "out_data";
}

SIGNAL("div_reg")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("div_reg[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div_reg";
}

SIGNAL("div_reg[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div_reg";
}

SIGNAL("div_reg[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div_reg";
}

SIGNAL("div_reg[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div_reg";
}

SIGNAL("div_reg[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div_reg";
}

SIGNAL("div_reg[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div_reg";
}

SIGNAL("div_reg[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div_reg";
}

SIGNAL("div_reg[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div_reg";
}

SIGNAL("div8_tras_reg")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 3;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("div8_tras_reg[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div8_tras_reg";
}

SIGNAL("div8_tras_reg[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div8_tras_reg";
}

SIGNAL("div8_tras_reg[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "div8_tras_reg";
}

SIGNAL("send_state")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 3;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("send_state[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "send_state";
}

SIGNAL("send_state[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "send_state";
}

SIGNAL("send_state[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "send_state";
}

SIGNAL("txd_buf")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("txd_buf[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "txd_buf";
}

SIGNAL("txd_buf[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "txd_buf";
}

SIGNAL("txd_buf[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "txd_buf";
}

SIGNAL("txd_buf[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "txd_buf";
}

SIGNAL("txd_buf[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "txd_buf";
}

SIGNAL("txd_buf[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "txd_buf";
}

SIGNAL("txd_buf[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "txd_buf";
}

SIGNAL("txd_buf[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "txd_buf";
}

SIGNAL("state_tras")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 4;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("state_tras[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "state_tras";
}

SIGNAL("state_tras[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "state_tras";
}

SIGNAL("state_tras[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "state_tras";
}

SIGNAL("state_tras[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "state_tras";
}

SIGNAL("trasstart")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "";
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 100000;
			LEVEL 0 FOR 500.0;
			LEVEL 1 FOR 500.0;
		}
	}
}

TRANSITION_LIST("key_input")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 61440.0;
		LEVEL 1 FOR 47124480.0;
		LEVEL 0 FOR 655360.0;
		LEVEL 1 FOR 52158720.0;
	}
}

TRANSITION_LIST("rst")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 61440.0;
		LEVEL 1 FOR 99938560.0;
	}
}

TRANSITION_LIST("rxd")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000000.0;
	}
}

TRANSITION_LIST("txd")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 502516.858;
		LEVEL 1 FOR 3744000.0;
		LEVEL 0 FOR 2964000.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 416000.0;
			LEVEL 0 FOR 416000.0;
		}
		LEVEL 1 FOR 832000.0;
		LEVEL 0 FOR 832000.0;
		LEVEL 1 FOR 416000.0;
		LEVEL 0 FOR 2964000.0;
		LEVEL 1 FOR 1248000.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 0 FOR 832000.0;
			LEVEL 1 FOR 416000.0;
		}
		LEVEL 0 FOR 2964000.0;
		LEVEL 1 FOR 416000.0;
		LEVEL 0 FOR 832000.0;
		LEVEL 1 FOR 1248000.0;
		LEVEL 0 FOR 832000.0;
		LEVEL 1 FOR 416000.0;
		LEVEL 0 FOR 2964000.0;
		LEVEL 1 FOR 416000.0;
		LEVEL 0 FOR 1664000.0;
		LEVEL 1 FOR 416000.0;
		LEVEL 0 FOR 832000.0;
		LEVEL 1 FOR 416000.0;
		LEVEL 0 FOR 2964000.0;
		LEVEL 1 FOR 416000.0;
		LEVEL 0 FOR 416000.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 416000.0;
			LEVEL 0 FOR 832000.0;
		}
		LEVEL 1 FOR 416000.0;
		LEVEL 0 FOR 2964000.0;
		NODE
		{
			REPEAT = 2;
			LEVEL 1 FOR 416000.0;
			LEVEL 0 FOR 416000.0;
		}
		LEVEL 1 FOR 832000.0;
		LEVEL 0 FOR 832000.0;
		LEVEL 1 FOR 416000.0;
		LEVEL 0 FOR 55505483.142;
	}
}

TRANSITION_LIST("en")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 100000000.0;
	}
}

TRANSITION_LIST("clkout")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 86513.42;
		NODE
		{
			REPEAT = 1921;
12 3 下一页
💿 文件大小 219 K
👤 上传用户 yuyx2003
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#VHDL #DTR #语言 #编写
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