urat.tan.qmsg

VHDL语言编写的全功能串口模块（包含DTR

{ "Info" "ITDB_TH_RESULT" "txd_reg key_input clk 4.393 ns register " "Info: th for register \"txd_reg\" (data pin = \"key_input\", clock pin = \"clk\") is 4.393 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.247 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns clk 1 CLK PIN_C7 9 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_C7; Fanout = 9; CLK Node = 'clk'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.198 ns) + CELL(0.935 ns) 7.608 ns clkbaud8x 2 REG LC_X11_Y8_N2 22 " "Info: 2: + IC(5.198 ns) + CELL(0.935 ns) = 7.608 ns; Loc. = LC_X11_Y8_N2; Fanout = 22; REG Node = 'clkbaud8x'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.133 ns" { clk clkbaud8x } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.928 ns) + CELL(0.711 ns) 12.247 ns txd_reg 3 REG LC_X20_Y12_N2 2 " "Info: 3: + IC(3.928 ns) + CELL(0.711 ns) = 12.247 ns; Loc. = LC_X20_Y12_N2; Fanout = 2; REG Node = 'txd_reg'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.639 ns" { clkbaud8x txd_reg } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.121 ns ( 25.48 % ) " "Info: Total cell delay = 3.121 ns ( 25.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.126 ns ( 74.52 % ) " "Info: Total interconnect delay = 9.126 ns ( 74.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x txd_reg } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x txd_reg } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.869 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.869 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns key_input 1 PIN PIN_G15 18 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_G15; Fanout = 18; PIN Node = 'key_input'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key_input } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.793 ns) + CELL(0.607 ns) 7.869 ns txd_reg 2 REG LC_X20_Y12_N2 2 " "Info: 2: + IC(5.793 ns) + CELL(0.607 ns) = 7.869 ns; Loc. = LC_X20_Y12_N2; Fanout = 2; REG Node = 'txd_reg'" {  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.400 ns" { key_input txd_reg } "NODE_NAME" } } { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns ( 26.38 % ) " "Info: Total cell delay = 2.076 ns ( 26.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.793 ns ( 73.62 % ) " "Info: Total interconnect delay = 5.793 ns ( 73.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.869 ns" { key_input txd_reg } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "7.869 ns" { key_input key_input~out0 txd_reg } { 0.000ns 0.000ns 5.793ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.247 ns" { clk clkbaud8x txd_reg } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "12.247 ns" { clk clk~out0 clkbaud8x txd_reg } { 0.000ns 0.000ns 5.198ns 3.928ns } { 0.000ns 1.475ns 0.935ns 0.711ns } } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.869 ns" { key_input txd_reg } "NODE_NAME" } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Technology_Viewer.qrui" "7.869 ns" { key_input key_input~out0 txd_reg } { 0.000ns 0.000ns 5.793ns } { 0.000ns 1.469ns 0.607ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 23 21:47:16 2007 " "Info: Processing ended: Fri Mar 23 21:47:16 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}