urat.tan.qmsg

来自「VHDL语言编写的全功能串口模块（包含DTR」· QMSG 代码 · 共 11 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 23 21:47:16 2007 " "Info: Processing started: Fri Mar 23 21:47:16 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off urat -c urat --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off urat -c urat --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "urat.vhd" "" { Text "E:/程序/uart/urat.vhd" 23 -1 0 } } { "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/tools/quartus ii 6.0/altera.quartus.ii.v6.0.repack-lz0/altera.quartus.ii.v6.0.repack-lz0/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}