std_2s60es.ptf

来自「Altera公司开发板2s60 CF卡通用例程（初始化、读、写、测试等）」· PTF 代码 · 共 2,116 行 · 第 1/5 页

            {
               format = "Logic";
               name = "F_vinst";
               radix = "ascii";
            }
            SIGNAL aba
            {
               format = "Logic";
               name = "D_vinst";
               radix = "ascii";
            }
            SIGNAL abb
            {
               format = "Logic";
               name = "E_vinst";
               radix = "ascii";
            }
            SIGNAL abc
            {
               format = "Logic";
               name = "M_vinst";
               radix = "ascii";
            }
            SIGNAL abd
            {
               format = "Logic";
               name = "W_vinst";
               radix = "ascii";
            }
            SIGNAL abe
            {
               format = "Logic";
               name = "F_inst_ram_hit";
               radix = "hexadecimal";
            }
            SIGNAL abf
            {
               format = "Logic";
               name = "F_issue";
               radix = "hexadecimal";
            }
            SIGNAL abg
            {
               format = "Logic";
               name = "F_kill";
               radix = "hexadecimal";
            }
            SIGNAL abh
            {
               format = "Logic";
               name = "D_kill";
               radix = "hexadecimal";
            }
            SIGNAL abi
            {
               format = "Logic";
               name = "D_refetch";
               radix = "hexadecimal";
            }
            SIGNAL abj
            {
               format = "Logic";
               name = "D_issue";
               radix = "hexadecimal";
            }
            SIGNAL abk
            {
               format = "Logic";
               name = "D_valid";
               radix = "hexadecimal";
            }
            SIGNAL abl
            {
               format = "Logic";
               name = "E_valid";
               radix = "hexadecimal";
            }
            SIGNAL abm
            {
               format = "Logic";
               name = "M_valid";
               radix = "hexadecimal";
            }
            SIGNAL abn
            {
               format = "Logic";
               name = "W_valid";
               radix = "hexadecimal";
            }
            SIGNAL abo
            {
               format = "Logic";
               name = "W_wr_dst_reg";
               radix = "hexadecimal";
            }
            SIGNAL abp
            {
               format = "Logic";
               name = "W_dst_regnum";
               radix = "hexadecimal";
            }
            SIGNAL abq
            {
               format = "Logic";
               name = "W_wr_data";
               radix = "hexadecimal";
            }
            SIGNAL abr
            {
               format = "Logic";
               name = "F_en";
               radix = "hexadecimal";
            }
            SIGNAL abs
            {
               format = "Logic";
               name = "D_en";
               radix = "hexadecimal";
            }
            SIGNAL abt
            {
               format = "Logic";
               name = "E_en";
               radix = "hexadecimal";
            }
            SIGNAL abu
            {
               format = "Logic";
               name = "M_en";
               radix = "hexadecimal";
            }
            SIGNAL abv
            {
               format = "Logic";
               name = "F_iw";
               radix = "hexadecimal";
            }
            SIGNAL abw
            {
               format = "Logic";
               name = "D_iw";
               radix = "hexadecimal";
            }
            SIGNAL abx
            {
               format = "Logic";
               name = "E_iw";
               radix = "hexadecimal";
            }
            SIGNAL aby
            {
               format = "Logic";
               name = "E_valid_prior_to_hbreak";
               radix = "hexadecimal";
            }
            SIGNAL abz
            {
               format = "Logic";
               name = "M_pipe_flush_nxt";
               radix = "hexadecimal";
            }
            SIGNAL aca
            {
               format = "Logic";
               name = "M_pipe_flush_baddr_nxt";
               radix = "hexadecimal";
            }
            SIGNAL acb
            {
               format = "Logic";
               name = "M_status_reg_pie";
               radix = "hexadecimal";
            }
            SIGNAL acc
            {
               format = "Logic";
               name = "M_ienable_reg";
               radix = "hexadecimal";
            }
            SIGNAL acd
            {
               format = "Logic";
               name = "intr_req";
               radix = "hexadecimal";
            }
         }
      }
      MASTER custom_instruction_master
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "nios_custom_instruction";
            Data_Width = "32";
            Address_Width = "8";
            Max_Address_Width = "8";
            Base_Address = "N/A";
            Is_Visible = "0";
            Is_Custom_Instruction = "0";
            Is_Enabled = "0";
         }
      }
      MASTER data_master2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "1";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Is_Readable = "1";
            Is_Writeable = "1";
            Address_Group = "0";
         }
      }
      MASTER data_channel_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER data_channel_master_1
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER data_channel_master_2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER data_channel_master_3
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER instruction_channel_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
         }
      }
      MASTER tightly_coupled_data_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Address_Group = "0";
         }
      }
      MASTER tightly_coupled_data_master_1
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Address_Group = "0";
         }
      }
      MASTER tightly_coupled_data_master_2
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Address_Group = "0";
         }
      }
      MASTER tightly_coupled_data_master_3
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Data_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";
            Is_Readable = "1";
            Is_Writeable = "1";
            Address_Group = "0";
         }
      }
      MASTER tightly_coupled_instruction_master_0
      {
         PORT_WIRING 
         {
         }
         SYSTEM_BUILDER_INFO 
         {
            Register_Incoming_Signals = "0";
            Bus_Type = "avalon";
            Data_Width = "32";
            Max_Address_Width = "31";
            Address_Width = "8";
            Is_Instruction_Master = "1";
            Has_IRQ = "0";
            Is_Enabled = "0";
            Connection_Limit = "1";
            Is_Channel = "1";