divclk.tan.qmsg

实用的任意时钟分频Verilog代码 可以任意分频的！

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 2 -1 0 } } { "e:/quartusii7.2/quartus/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartusii7.2/quartus/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register s1\[1\] register s1\[96\] 128.04 MHz 7.81 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 128.04 MHz between source register \"s1\[1\]\" and destination register \"s1\[96\]\" (period= 7.81 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.529 ns + Longest register register " "Info: + Longest register to register delay is 7.529 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns s1\[1\] 1 REG LC_X20_Y16_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y16_N2; Fanout = 4; REG Node = 's1\[1\]'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { s1[1] } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.257 ns) + CELL(0.423 ns) 1.680 ns Add0~1498 2 COMB LC_X21_Y17_N1 2 " "Info: 2: + IC(1.257 ns) + CELL(0.423 ns) = 1.680 ns; Loc. = LC_X21_Y17_N1; Fanout = 2; COMB Node = 'Add0~1498'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.680 ns" { s1[1] Add0~1498 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.758 ns Add0~1502 3 COMB LC_X21_Y17_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.758 ns; Loc. = LC_X21_Y17_N2; Fanout = 2; COMB Node = 'Add0~1502'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { Add0~1498 Add0~1502 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.836 ns Add0~1504 4 COMB LC_X21_Y17_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.836 ns; Loc. = LC_X21_Y17_N3; Fanout = 2; COMB Node = 'Add0~1504'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { Add0~1502 Add0~1504 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 2.014 ns Add0~1506 5 COMB LC_X21_Y17_N4 6 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 2.014 ns; Loc. = LC_X21_Y17_N4; Fanout = 6; COMB Node = 'Add0~1506'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { Add0~1504 Add0~1506 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.222 ns Add0~1516 6 COMB LC_X21_Y17_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.208 ns) = 2.222 ns; Loc. = LC_X21_Y17_N9; Fanout = 6; COMB Node = 'Add0~1516'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Add0~1506 Add0~1516 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.358 ns Add0~1526 7 COMB LC_X21_Y16_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.358 ns; Loc. = LC_X21_Y16_N4; Fanout = 6; COMB Node = 'Add0~1526'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { Add0~1516 Add0~1526 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.566 ns Add0~1536 8 COMB LC_X21_Y16_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 2.566 ns; Loc. = LC_X21_Y16_N9; Fanout = 6; COMB Node = 'Add0~1536'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Add0~1526 Add0~1536 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.702 ns Add0~1546 9 COMB LC_X21_Y15_N4 6 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 2.702 ns; Loc. = LC_X21_Y15_N4; Fanout = 6; COMB Node = 'Add0~1546'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { Add0~1536 Add0~1546 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.910 ns Add0~1556 10 COMB LC_X21_Y15_N9 6 " "Info: 10: + IC(0.000 ns) + CELL(0.208 ns) = 2.910 ns; Loc. = LC_X21_Y15_N9; Fanout = 6; COMB Node = 'Add0~1556'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Add0~1546 Add0~1556 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 3.046 ns Add0~1566 11 COMB LC_X21_Y14_N4 6 " "Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 3.046 ns; Loc. = LC_X21_Y14_N4; Fanout = 6; COMB Node = 'Add0~1566'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { Add0~1556 Add0~1566 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 3.254 ns Add0~1576 12 COMB LC_X21_Y14_N9 6 " "Info: 12: + IC(0.000 ns) + CELL(0.208 ns) = 3.254 ns; Loc. = LC_X21_Y14_N9; Fanout = 6; COMB Node = 'Add0~1576'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Add0~1566 Add0~1576 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 3.390 ns Add0~1586 13 COMB LC_X21_Y13_N4 6 " "Info: 13: + IC(0.000 ns) + CELL(0.136 ns) = 3.390 ns; Loc. = LC_X21_Y13_N4; Fanout = 6; COMB Node = 'Add0~1586'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { Add0~1576 Add0~1586 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 3.598 ns Add0~1596 14 COMB LC_X21_Y13_N9 6 " "Info: 14: + IC(0.000 ns) + CELL(0.208 ns) = 3.598 ns; Loc. = LC_X21_Y13_N9; Fanout = 6; COMB Node = 'Add0~1596'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Add0~1586 Add0~1596 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 3.734 ns Add0~1606 15 COMB LC_X21_Y12_N4 6 " "Info: 15: + IC(0.000 ns) + CELL(0.136 ns) = 3.734 ns; Loc. = LC_X21_Y12_N4; Fanout = 6; COMB Node = 'Add0~1606'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { Add0~1596 Add0~1606 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 3.942 ns Add0~1616 16 COMB LC_X21_Y12_N9 6 " "Info: 16: + IC(0.000 ns) + CELL(0.208 ns) = 3.942 ns; Loc. = LC_X21_Y12_N9; Fanout = 6; COMB Node = 'Add0~1616'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Add0~1606 Add0~1616 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 4.078 ns Add0~1626 17 COMB LC_X21_Y11_N4 6 " "Info: 17: + IC(0.000 ns) + CELL(0.136 ns) = 4.078 ns; Loc. = LC_X21_Y11_N4; Fanout = 6; COMB Node = 'Add0~1626'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { Add0~1616 Add0~1626 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 4.286 ns Add0~1636 18 COMB LC_X21_Y11_N9 6 " "Info: 18: + IC(0.000 ns) + CELL(0.208 ns) = 4.286 ns; Loc. = LC_X21_Y11_N9; Fanout = 6; COMB Node = 'Add0~1636'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Add0~1626 Add0~1636 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 4.422 ns Add0~1646 19 COMB LC_X21_Y10_N4 6 " "Info: 19: + IC(0.000 ns) + CELL(0.136 ns) = 4.422 ns; Loc. = LC_X21_Y10_N4; Fanout = 6; COMB Node = 'Add0~1646'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { Add0~1636 Add0~1646 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 4.630 ns Add0~1656 20 COMB LC_X21_Y10_N9 6 " "Info: 20: + IC(0.000 ns) + CELL(0.208 ns) = 4.630 ns; Loc. = LC_X21_Y10_N9; Fanout = 6; COMB Node = 'Add0~1656'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Add0~1646 Add0~1656 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 4.766 ns Add0~1666 21 COMB LC_X21_Y9_N4 6 " "Info: 21: + IC(0.000 ns) + CELL(0.136 ns) = 4.766 ns; Loc. = LC_X21_Y9_N4; Fanout = 6; COMB Node = 'Add0~1666'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { Add0~1656 Add0~1666 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 4.974 ns Add0~1676 22 COMB LC_X21_Y9_N9 6 " "Info: 22: + IC(0.000 ns) + CELL(0.208 ns) = 4.974 ns; Loc. = LC_X21_Y9_N9; Fanout = 6; COMB Node = 'Add0~1676'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { Add0~1666 Add0~1676 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 5.110 ns Add0~1686 23 COMB LC_X21_Y8_N4 5 " "Info: 23: + IC(0.000 ns) + CELL(0.136 ns) = 5.110 ns; Loc. = LC_X21_Y8_N4; Fanout = 5; COMB Node = 'Add0~1686'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { Add0~1676 Add0~1686 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 5.731 ns Add0~1689 24 COMB LC_X21_Y8_N6 1 " "Info: 24: + IC(0.000 ns) + CELL(0.621 ns) = 5.731 ns; Loc. = LC_X21_Y8_N6; Fanout = 1; COMB Node = 'Add0~1689'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.621 ns" { Add0~1686 Add0~1689 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.683 ns) + CELL(0.115 ns) 7.529 ns s1\[96\] 25 REG LC_X20_Y12_N8 4 " "Info: 25: + IC(1.683 ns) + CELL(0.115 ns) = 7.529 ns; Loc. = LC_X20_Y12_N8; Fanout = 4; REG Node = 's1\[96\]'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.798 ns" { Add0~1689 s1[96] } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.589 ns ( 60.95 % ) " "Info: Total cell delay = 4.589 ns ( 60.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.940 ns ( 39.05 % ) " "Info: Total interconnect delay = 2.940 ns ( 39.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.529 ns" { s1[1] Add0~1498 Add0~1502 Add0~1504 Add0~1506 Add0~1516 Add0~1526 Add0~1536 Add0~1546 Add0~1556 Add0~1566 Add0~1576 Add0~1586 Add0~1596 Add0~1606 Add0~1616 Add0~1626 Add0~1636 Add0~1646 Add0~1656 Add0~1666 Add0~1676 Add0~1686 Add0~1689 s1[96] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "7.529 ns" { s1[1] {} Add0~1498 {} Add0~1502 {} Add0~1504 {} Add0~1506 {} Add0~1516 {} Add0~1526 {} Add0~1536 {} Add0~1546 {} Add0~1556 {} Add0~1566 {} Add0~1576 {} Add0~1586 {} Add0~1596 {} Add0~1606 {} Add0~1616 {} Add0~1626 {} Add0~1636 {} Add0~1646 {} Add0~1656 {} Add0~1666 {} Add0~1676 {} Add0~1686 {} Add0~1689 {} s1[96] {} } { 0.000ns 1.257ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.683ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.621ns 0.115ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.942 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk1 1 CLK PIN_153 101 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 101; CLK Node = 'clk1'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns s1\[96\] 2 REG LC_X20_Y12_N8 4 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X20_Y12_N8; Fanout = 4; REG Node = 's1\[96\]'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { clk1 s1[96] } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk1 s1[96] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk1 {} clk1~out0 {} s1[96] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.962 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 2.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk1 1 CLK PIN_153 101 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 101; CLK Node = 'clk1'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.711 ns) 2.962 ns s1\[1\] 2 REG LC_X20_Y16_N2 4 " "Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X20_Y16_N2; Fanout = 4; REG Node = 's1\[1\]'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.493 ns" { clk1 s1[1] } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 73.60 % ) " "Info: Total cell delay = 2.180 ns ( 73.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.782 ns ( 26.40 % ) " "Info: Total interconnect delay = 0.782 ns ( 26.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk1 s1[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk1 {} clk1~out0 {} s1[1] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk1 s1[96] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk1 {} clk1~out0 {} s1[96] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk1 s1[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk1 {} clk1~out0 {} s1[1] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "7.529 ns" { s1[1] Add0~1498 Add0~1502 Add0~1504 Add0~1506 Add0~1516 Add0~1526 Add0~1536 Add0~1546 Add0~1556 Add0~1566 Add0~1576 Add0~1586 Add0~1596 Add0~1606 Add0~1616 Add0~1626 Add0~1636 Add0~1646 Add0~1656 Add0~1666 Add0~1676 Add0~1686 Add0~1689 s1[96] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "7.529 ns" { s1[1] {} Add0~1498 {} Add0~1502 {} Add0~1504 {} Add0~1506 {} Add0~1516 {} Add0~1526 {} Add0~1536 {} Add0~1546 {} Add0~1556 {} Add0~1566 {} Add0~1576 {} Add0~1586 {} Add0~1596 {} Add0~1606 {} Add0~1616 {} Add0~1626 {} Add0~1636 {} Add0~1646 {} Add0~1656 {} Add0~1666 {} Add0~1676 {} Add0~1686 {} Add0~1689 {} s1[96] {} } { 0.000ns 1.257ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.683ns } { 0.000ns 0.423ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.621ns 0.115ns } "" } } { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk1 s1[96] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk1 {} clk1~out0 {} s1[96] {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.962 ns" { clk1 s1[1] } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "2.962 ns" { clk1 {} clk1~out0 {} s1[1] {} } { 0.000ns 0.000ns 0.782ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 clk2 clk2~reg0 9.064 ns register " "Info: tco from clock \"clk1\" to destination pin \"clk2\" through register \"clk2~reg0\" is 9.064 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.942 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 2.942 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk1 1 CLK PIN_153 101 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 101; CLK Node = 'clk1'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.711 ns) 2.942 ns clk2~reg0 2 REG LC_X20_Y12_N3 2 " "Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X20_Y12_N3; Fanout = 2; REG Node = 'clk2~reg0'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.473 ns" { clk1 clk2~reg0 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 74.10 % ) " "Info: Total cell delay = 2.180 ns ( 74.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.762 ns ( 25.90 % ) " "Info: Total interconnect delay = 0.762 ns ( 25.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk1 clk2~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk1 {} clk1~out0 {} clk2~reg0 {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.898 ns + Longest register pin " "Info: + Longest register to pin delay is 5.898 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk2~reg0 1 REG LC_X20_Y12_N3 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y12_N3; Fanout = 2; REG Node = 'clk2~reg0'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk2~reg0 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.774 ns) + CELL(2.124 ns) 5.898 ns clk2 2 PIN PIN_7 0 " "Info: 2: + IC(3.774 ns) + CELL(2.124 ns) = 5.898 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'clk2'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.898 ns" { clk2~reg0 clk2 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 36.01 % ) " "Info: Total cell delay = 2.124 ns ( 36.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.774 ns ( 63.99 % ) " "Info: Total interconnect delay = 3.774 ns ( 63.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.898 ns" { clk2~reg0 clk2 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "5.898 ns" { clk2~reg0 {} clk2 {} } { 0.000ns 3.774ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "2.942 ns" { clk1 clk2~reg0 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "2.942 ns" { clk1 {} clk1~out0 {} clk2~reg0 {} } { 0.000ns 0.000ns 0.762ns } { 0.000ns 1.469ns 0.711ns } "" } } { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "5.898 ns" { clk2~reg0 clk2 } "NODE_NAME" } } { "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartusii7.2/quartus/quartus/bin/Technology_Viewer.qrui" "5.898 ns" { clk2~reg0 {} clk2 {} } { 0.000ns 3.774ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}