divclk.fit.qmsg

实用的任意时钟分频Verilog代码 可以任意分频的！

{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0 0 "Finished moving registers into I/O cells, LUTs, and RAM blocks" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.855 ns register register " "Info: Estimated most critical path is register to register delay of 6.855 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns s1\[11\] 1 REG LAB_X22_Y18 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X22_Y18; Fanout = 4; REG Node = 's1\[11\]'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "" { s1[11] } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.114 ns) 1.788 ns Equal0~2009 2 COMB LAB_X20_Y17 1 " "Info: 2: + IC(1.674 ns) + CELL(0.114 ns) = 1.788 ns; Loc. = LAB_X20_Y17; Fanout = 1; COMB Node = 'Equal0~2009'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.788 ns" { s1[11] Equal0~2009 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 2.441 ns Equal0~2011 3 COMB LAB_X20_Y17 1 " "Info: 3: + IC(0.361 ns) + CELL(0.292 ns) = 2.441 ns; Loc. = LAB_X20_Y17; Fanout = 1; COMB Node = 'Equal0~2011'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { Equal0~2009 Equal0~2011 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.193 ns) + CELL(0.590 ns) 4.224 ns Equal0~2027 4 COMB LAB_X20_Y12 1 " "Info: 4: + IC(1.193 ns) + CELL(0.590 ns) = 4.224 ns; Loc. = LAB_X20_Y12; Fanout = 1; COMB Node = 'Equal0~2027'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.783 ns" { Equal0~2011 Equal0~2027 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.063 ns) + CELL(0.590 ns) 4.877 ns Equal0~2039 5 COMB LAB_X20_Y12 7 " "Info: 5: + IC(0.063 ns) + CELL(0.590 ns) = 4.877 ns; Loc. = LAB_X20_Y12; Fanout = 7; COMB Node = 'Equal0~2039'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "0.653 ns" { Equal0~2027 Equal0~2039 } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.669 ns) + CELL(0.309 ns) 6.855 ns s1\[0\] 6 REG LAB_X20_Y17 4 " "Info: 6: + IC(1.669 ns) + CELL(0.309 ns) = 6.855 ns; Loc. = LAB_X20_Y17; Fanout = 4; REG Node = 's1\[0\]'" {  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "1.978 ns" { Equal0~2039 s1[0] } "NODE_NAME" } } { "divclk.v" "" { Text "D:/电子/FPGA学习/华清练习/divclk/divclk.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.895 ns ( 27.64 % ) " "Info: Total cell delay = 1.895 ns ( 27.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.960 ns ( 72.36 % ) " "Info: Total interconnect delay = 4.960 ns ( 72.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartusii7.2/quartus/quartus/bin/TimingClosureFloorplan.fld" "" "6.855 ns" { s1[11] Equal0~2009 Equal0~2011 Equal0~2027 Equal0~2039 s1[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X12_Y11 X23_Y21 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X12_Y11 to location X23_Y21" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/电子/FPGA学习/华清练习/divclk/divclk.fit.smsg " "Info: Generated suppressed messages file D:/电子/FPGA学习/华清练习/divclk/divclk.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "174 " "Info: Allocated 174 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 15 14:53:15 2008 " "Info: Processing ended: Fri Aug 15 14:53:15 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}