divclk.map.summary

来自「实用的任意时钟分频Verilog代码 可以任意分频的！」· SUMMARY 代码 · 共 13 行

Analysis & Synthesis Status : Successful - Fri Aug 15 14:53:11 2008
Quartus II Version : 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
Revision Name : divclk
Top-level Entity Name : divclk
Family : Cyclone
Total logic elements : 234
Total pins : 2
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge