divclk.tan.rpt

实用的任意时钟分频Verilog代码 可以任意分频的！

; N/A                                     ; 147.84 MHz ( period = 6.764 ns )                    ; s1[4]  ; s1[93] ; clk1       ; clk1     ; None                        ; None                      ; 6.450 ns                ;
; N/A                                     ; 147.93 MHz ( period = 6.760 ns )                    ; s1[0]  ; s1[92] ; clk1       ; clk1     ; None                        ; None                      ; 6.446 ns                ;
; N/A                                     ; 147.93 MHz ( period = 6.760 ns )                    ; s1[5]  ; s1[93] ; clk1       ; clk1     ; None                        ; None                      ; 6.446 ns                ;
; N/A                                     ; 147.93 MHz ( period = 6.760 ns )                    ; s1[8]  ; s1[99] ; clk1       ; clk1     ; None                        ; None                      ; 6.479 ns                ;
; N/A                                     ; 147.95 MHz ( period = 6.759 ns )                    ; s1[8]  ; s1[98] ; clk1       ; clk1     ; None                        ; None                      ; 6.478 ns                ;
; N/A                                     ; 147.97 MHz ( period = 6.758 ns )                    ; s1[15] ; s1[81] ; clk1       ; clk1     ; None                        ; None                      ; 6.444 ns                ;
; N/A                                     ; 148.04 MHz ( period = 6.755 ns )                    ; s1[10] ; s1[99] ; clk1       ; clk1     ; None                        ; None                      ; 6.474 ns                ;
; N/A                                     ; 148.06 MHz ( period = 6.754 ns )                    ; s1[10] ; s1[98] ; clk1       ; clk1     ; None                        ; None                      ; 6.473 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;        ;        ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+--------+--------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 9.064 ns   ; clk2~reg0 ; clk2 ; clk1       ;
+-------+--------------+------------+-----------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Full Version
    Info: Processing started: Fri Aug 15 14:53:20 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off divclk -c divclk --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk1" is an undefined clock
Info: Clock "clk1" has Internal fmax of 128.04 MHz between source register "s1[1]" and destination register "s1[96]" (period= 7.81 ns)
    Info: + Longest register to register delay is 7.529 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y16_N2; Fanout = 4; REG Node = 's1[1]'
        Info: 2: + IC(1.257 ns) + CELL(0.423 ns) = 1.680 ns; Loc. = LC_X21_Y17_N1; Fanout = 2; COMB Node = 'Add0~1498'
        Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.758 ns; Loc. = LC_X21_Y17_N2; Fanout = 2; COMB Node = 'Add0~1502'
        Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.836 ns; Loc. = LC_X21_Y17_N3; Fanout = 2; COMB Node = 'Add0~1504'
        Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 2.014 ns; Loc. = LC_X21_Y17_N4; Fanout = 6; COMB Node = 'Add0~1506'
        Info: 6: + IC(0.000 ns) + CELL(0.208 ns) = 2.222 ns; Loc. = LC_X21_Y17_N9; Fanout = 6; COMB Node = 'Add0~1516'
        Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 2.358 ns; Loc. = LC_X21_Y16_N4; Fanout = 6; COMB Node = 'Add0~1526'
        Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 2.566 ns; Loc. = LC_X21_Y16_N9; Fanout = 6; COMB Node = 'Add0~1536'
        Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 2.702 ns; Loc. = LC_X21_Y15_N4; Fanout = 6; COMB Node = 'Add0~1546'
        Info: 10: + IC(0.000 ns) + CELL(0.208 ns) = 2.910 ns; Loc. = LC_X21_Y15_N9; Fanout = 6; COMB Node = 'Add0~1556'
        Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 3.046 ns; Loc. = LC_X21_Y14_N4; Fanout = 6; COMB Node = 'Add0~1566'
        Info: 12: + IC(0.000 ns) + CELL(0.208 ns) = 3.254 ns; Loc. = LC_X21_Y14_N9; Fanout = 6; COMB Node = 'Add0~1576'
        Info: 13: + IC(0.000 ns) + CELL(0.136 ns) = 3.390 ns; Loc. = LC_X21_Y13_N4; Fanout = 6; COMB Node = 'Add0~1586'
        Info: 14: + IC(0.000 ns) + CELL(0.208 ns) = 3.598 ns; Loc. = LC_X21_Y13_N9; Fanout = 6; COMB Node = 'Add0~1596'
        Info: 15: + IC(0.000 ns) + CELL(0.136 ns) = 3.734 ns; Loc. = LC_X21_Y12_N4; Fanout = 6; COMB Node = 'Add0~1606'
        Info: 16: + IC(0.000 ns) + CELL(0.208 ns) = 3.942 ns; Loc. = LC_X21_Y12_N9; Fanout = 6; COMB Node = 'Add0~1616'
        Info: 17: + IC(0.000 ns) + CELL(0.136 ns) = 4.078 ns; Loc. = LC_X21_Y11_N4; Fanout = 6; COMB Node = 'Add0~1626'
        Info: 18: + IC(0.000 ns) + CELL(0.208 ns) = 4.286 ns; Loc. = LC_X21_Y11_N9; Fanout = 6; COMB Node = 'Add0~1636'
        Info: 19: + IC(0.000 ns) + CELL(0.136 ns) = 4.422 ns; Loc. = LC_X21_Y10_N4; Fanout = 6; COMB Node = 'Add0~1646'
        Info: 20: + IC(0.000 ns) + CELL(0.208 ns) = 4.630 ns; Loc. = LC_X21_Y10_N9; Fanout = 6; COMB Node = 'Add0~1656'
        Info: 21: + IC(0.000 ns) + CELL(0.136 ns) = 4.766 ns; Loc. = LC_X21_Y9_N4; Fanout = 6; COMB Node = 'Add0~1666'
        Info: 22: + IC(0.000 ns) + CELL(0.208 ns) = 4.974 ns; Loc. = LC_X21_Y9_N9; Fanout = 6; COMB Node = 'Add0~1676'
        Info: 23: + IC(0.000 ns) + CELL(0.136 ns) = 5.110 ns; Loc. = LC_X21_Y8_N4; Fanout = 5; COMB Node = 'Add0~1686'
        Info: 24: + IC(0.000 ns) + CELL(0.621 ns) = 5.731 ns; Loc. = LC_X21_Y8_N6; Fanout = 1; COMB Node = 'Add0~1689'
        Info: 25: + IC(1.683 ns) + CELL(0.115 ns) = 7.529 ns; Loc. = LC_X20_Y12_N8; Fanout = 4; REG Node = 's1[96]'
        Info: Total cell delay = 4.589 ns ( 60.95 % )
        Info: Total interconnect delay = 2.940 ns ( 39.05 % )
    Info: - Smallest clock skew is -0.020 ns
        Info: + Shortest clock path from clock "clk1" to destination register is 2.942 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 101; CLK Node = 'clk1'
            Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X20_Y12_N8; Fanout = 4; REG Node = 's1[96]'
            Info: Total cell delay = 2.180 ns ( 74.10 % )
            Info: Total interconnect delay = 0.762 ns ( 25.90 % )
        Info: - Longest clock path from clock "clk1" to source register is 2.962 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 101; CLK Node = 'clk1'
            Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X20_Y16_N2; Fanout = 4; REG Node = 's1[1]'
            Info: Total cell delay = 2.180 ns ( 73.60 % )
            Info: Total interconnect delay = 0.782 ns ( 26.40 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk1" to destination pin "clk2" through register "clk2~reg0" is 9.064 ns
    Info: + Longest clock path from clock "clk1" to source register is 2.942 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 101; CLK Node = 'clk1'
        Info: 2: + IC(0.762 ns) + CELL(0.711 ns) = 2.942 ns; Loc. = LC_X20_Y12_N3; Fanout = 2; REG Node = 'clk2~reg0'
        Info: Total cell delay = 2.180 ns ( 74.10 % )
        Info: Total interconnect delay = 0.762 ns ( 25.90 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.898 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X20_Y12_N3; Fanout = 2; REG Node = 'clk2~reg0'
        Info: 2: + IC(3.774 ns) + CELL(2.124 ns) = 5.898 ns; Loc. = PIN_7; Fanout = 0; PIN Node = 'clk2'
        Info: Total cell delay = 2.124 ns ( 36.01 % )
        Info: Total interconnect delay = 3.774 ns ( 63.99 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 112 megabytes of memory during processing
    Info: Processing ended: Fri Aug 15 14:53:20 2008
    Info: Elapsed time: 00:00:00